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authorMichael Sevakis <jethead71@rockbox.org>2008-12-04 15:06:48 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-12-04 15:06:48 +0000
commita1ab7a55ffc768da55e4cb30a87cfb85b1231902 (patch)
treec64c6bdaa07fb7dd522ae96aa8c3543758dd68d1 /firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c
parent7bc50d1aa545bfed89e1e8f4f0446f9b9da65a3a (diff)
Meg-FX: s3c register definitions really should be unsigned. Switch from 'int' to 'unsigned long' like other targets.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c')
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c
index 8300944243..836dedd462 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count)
mutex_lock(&i2c_mtx);
/* Turn on I2C clock */
- s3c_regset(&CLKCON, 1 << 16);
+ s3c_regset32(&CLKCON, 1 << 16);
/* Set mode to master transmitter and enable lines */
IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB;
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count)
IICSTAT = 0;
/* Turn off I2C clock */
- s3c_regclr(&CLKCON, 1 << 16);
+ s3c_regclr32(&CLKCON, 1 << 16);
mutex_unlock(&i2c_mtx);
}
@@ -92,11 +92,11 @@ void i2c_init(void)
INTPND = IIC_MASK;
/* Enable i2c interrupt in controller */
- s3c_regclr(&INTMOD, IIC_MASK);
- s3c_regclr(&INTMSK, IIC_MASK);
+ s3c_regclr32(&INTMOD, IIC_MASK);
+ s3c_regclr32(&INTMSK, IIC_MASK);
/* Turn on I2C clock */
- s3c_regset(&CLKCON, 1 << 16);
+ s3c_regset32(&CLKCON, 1 << 16);
/* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */
GPECON = (GPECON & ~((3 << 30) | (3 << 28))) |
@@ -110,7 +110,7 @@ void i2c_init(void)
IICLC = (0 << 0);
/* Turn off I2C clock */
- s3c_regclr(&CLKCON, 1 << 16);
+ s3c_regclr32(&CLKCON, 1 << 16);
}
void IIC(void)