as3525v2: assume plla is the source for pclk (verified with timer frequency)

The frequencies are correctly displayed in the debug menu

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25418 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 12 insertions, 3 deletions

diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 2feef89095..aace5eb620 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -70,7 +70,11 @@
 #define AS3525_FCLK_FREQ        AS3525_PLLA_FREQ
 
 /* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), but if we use
- * the same frequency for DRAM & PCLK it's not a problem as the bit is unset */
+ * the same frequency for DRAM & PCLK it's not a problem as the bit is unset
+ *
+ * Note that setting bits 1:0 have no effect and they always read back as 0
+ * Perhaps it means CGU_PERI defaults to PLLA as source ?
+ */
 #define AS3525_DRAM_FREQ        60000000    /* Initial DRAM frequency  */
 #define AS3525_PCLK_FREQ        AS3525_DRAM_FREQ/1
 
diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c
index d2e6f3c658..5c135cc10d 100644
--- a/firmware/target/arm/as3525/debug-as3525.c
+++ b/firmware/target/arm/as3525/debug-as3525.c
@@ -143,7 +143,13 @@ static int calc_freq(int clk)
                     return 0;
             }
         case CLK_EXTMEM:
+        /* bits 1:0 of CGU_PERI always read as 0 and we assume source = PLLA */
+#if CONFIG_CPU == AS3525
             switch(CGU_PERI & 3) {
+#else
+        /* bits 1:0 of CGU_PERI always read as 0 and we assume source = PLLA */
+            switch(1) {
+#endif
                 case 0:
                     return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
                 case 1:
@@ -151,9 +157,8 @@ static int calc_freq(int clk)
                 case 2:
                     return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
                 case 3:
-                    return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
                 default:
-                    return 0;
+                    return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
             }
         case CLK_PCLK:
             return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);