diff options
| author | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-01 04:37:17 +0000 |
|---|---|---|
| committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-01 04:37:17 +0000 |
| commit | a28a9210d016be20baed743337b8da0b8338aa33 (patch) | |
| tree | 38232a313b5ba3cd6ff9689617a5979e9228f383 /firmware | |
| parent | 49935f2fa8d4869a8b32586b2326af35959920e0 (diff) | |
Fix boosting on as3525v2
the arm926-ejs doesn't have synchronous/asynchronous/fastbus modes, so
just change CGU_PROC directly
Note: we could use a lower unboosted frequency now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25417 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 1 | ||||
| -rw-r--r-- | firmware/target/arm/as3525/debug-as3525.c | 8 | ||||
| -rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 13 |
3 files changed, 19 insertions, 3 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 9bb20b21ad..2feef89095 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -120,6 +120,7 @@ /* FCLK */ #define AS3525_FCLK_SEL AS3525_CLK_PLLA #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) : needed for as3525v2 */ /* MCLK */ #define AS3525_MCLK_SEL AS3525_CLK_PLLA diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c index 0e09464c3d..d2e6f3c658 100644 --- a/firmware/target/arm/as3525/debug-as3525.c +++ b/firmware/target/arm/as3525/debug-as3525.c @@ -123,9 +123,11 @@ static int calc_freq(int clk) return 0; #endif case CLK_PROC: +#if CONFIG_CPU == AS3525 /* not in arm926-ejs */ if (!(read_cp15()>>30)) /* fastbus */ return calc_freq(CLK_PCLK); else /* Synch or Asynch bus*/ +#endif /* CONFIG_CPU == AS3525 */ return calc_freq(CLK_FCLK); case CLK_FCLK: switch(CGU_PROC & 3) { @@ -256,11 +258,11 @@ bool __dbg_hw_info(void) lcd_puts(0, line++, " SET ACTUAL"); #if CONFIG_CPU == AS3525 lcd_putsf(0, line++, "922T:%s %3dMHz", -#else - lcd_putsf(0, line++, "926ejs:%s %3dMHz", -#endif (!(read_cp15()>>30)) ? "FAST " : (read_cp15()>>31) ? "ASYNC" : "SYNC ", +#else + lcd_putsf(0, line++, "926ejs: %3dMHz", +#endif calc_freq(CLK_PROC)/1000000); lcd_putsf(0, line++, "PLLA:%3dMHz %3dMHz", AS3525_PLLA_FREQ/1000000, calc_freq(CLK_PLLA)/1000000); diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 201143c0ef..55c309ed44 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c @@ -257,6 +257,7 @@ void system_init(void) CGU_PROC = 0; /* fclk 24 MHz */ CGU_PERI &= ~0x7f; /* pclk 24 MHz */ + /* bits 31:30 should be set to 0 in arm926-ejs */ asm volatile( "mrc p15, 0, r0, c1, c0 \n" /* control register */ "bic r0, r0, #3<<30 \n" /* clears bus bits : sets fastbus */ @@ -351,6 +352,7 @@ void set_cpu_frequency(long frequency) while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */ #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */ +#if CONFIG_CPU == AS3525 /* only in arm922tdmi */ asm volatile( "mrc p15, 0, r0, c1, c0 \n" @@ -363,16 +365,27 @@ void set_cpu_frequency(long frequency) "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); +#else + CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | + (AS3525_FCLK_PREDIV << 2) | + AS3525_FCLK_SEL); +#endif /* CONFIG_CPU == AS3525 */ cpu_frequency = CPUFREQ_MAX; } else { +#if CONFIG_CPU == AS3525 /* only in arm922tdmi */ asm volatile( "mrc p15, 0, r0, c1, c0 \n" "bic r0, r0, #3<<30 \n" /* fastbus clocking */ "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); +#else + CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) | + (AS3525_FCLK_PREDIV << 2) | + AS3525_FCLK_SEL); +#endif /* CONFIG_CPU == AS3525 */ #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE /* Decreasing frequency so reduce voltage after change */ |