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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2015-04-28drm/i915/chv: Implement WaDisableShadowRegForCpdDeepak S
2015-04-23drm/i915: cope with large i2c transfersDmitry Torokhov
2015-03-25drm/i915: Add fault address to error state for gen8 and gen9Mika Kuoppala
2015-03-20drm/i915: Use down ei for manual Baytrail RPS calculationsChris Wilson
2015-03-20drm/i915: Improved w/a for rps on BaytrailChris Wilson
2015-03-17drm/i915/skl: Added new macrosAkash Goel
2015-03-17drm/i915: Use FW_WM() macro for older gmch platforms tooVille Syrjälä
2015-03-17drm/i915: Add polish to VLV WM shift+mask operationsVille Syrjälä
2015-03-17drm/i915: Disable DDR DVFS on CHVVille Syrjälä
2015-03-17drm/i915: Enable the maxfifo PM5 mode when appropriate on CHVVille Syrjälä
2015-03-17drm/i915: Program PFI credits for VLVVidya Srinivas
2015-03-17drm/i915: Rewrite VLV/CHV watermark codeVille Syrjälä
2015-03-17drm/i915: Update prop, int co-eff and gain threshold for CHVVijay Purushothaman
2015-03-17drm/i915: Initialize CHV digital lock detect thresholdVijay Purushothaman
2015-03-17drm/i915: Disable M2 frac division for integer caseVijay Purushothaman
2015-03-17drm/i915/chv: Add CHV HW status to SSEU statusJeff McGee
2015-03-17drm/i915/chv: Determine CHV slice/subslice/EU infoJeff McGee
2015-03-17drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä
2015-03-17drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä
2015-03-17drm/i915: Hide VLV DDL precision handlingVille Syrjälä
2015-03-17drm/i915: Kill DRAIN_LATENCY_PRECISION_* definesVille Syrjälä
2015-03-17drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä
2015-03-17drm/i915: Fix trivial typos in comments and warning messageYannick Guerrini
2015-02-24drm/i915: Support for RR switching on VLVVandana Kannan
2015-02-24drm/i915/skl: Tune IZ hashing when subslices are unbalancedDamien Lespiau
2015-02-23drm/i915: Request full SSEU enablement on Gen9Jeff McGee
2015-02-23drm/i915/skl: Add SKL HW status to SSEU statusJeff McGee
2015-02-23drm/i915/skl: Determine SKL slice/subslice/EU infoJeff McGee
2015-02-23drm/i915/skl: Implement WaDisablePowerCompilerClockGatingDamien Lespiau
2015-02-23drm/i915: Add new PHY reg definitions for lock thresholdVijay Purushothaman
2015-02-13drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrementDamien Lespiau
2015-02-13drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChickenDamien Lespiau
2015-02-13drm/i915/skl: Implement WaBarrierPerformanceFixDisableDamien Lespiau
2015-02-13drm/i915/skl: Implement WaCcsTlbPrefetchDisable:sklDamien Lespiau
2015-02-13drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCSDamien Lespiau
2015-02-13drm/i915/skl: Implement WaDisableHDCInvalidationDamien Lespiau
2015-02-13drm/i915/skl: Implement WaDisableLSQCROPERFforOCLDamien Lespiau
2015-02-13drm/i915/skl: Implement WaDisablePartialResolveInVcDamien Lespiau
2015-02-13drm/i915/skl: Implement WaSetGAPSunitClckGateDisableDamien Lespiau
2015-02-13drm/i915: Detect eDRAM with the enabled bit onlyDamien Lespiau
2015-02-13drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherentDamien Lespiau
2015-02-13drm/i915/gen9: Implement WaEnableYV12BugFixInHalfSliceChicken7Nick Hoath
2015-02-13drm/i915/gen9: h/w w/a: syncing dependencies between camera and graphicsNick Hoath
2015-02-13drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M
2015-01-28drm/i915/skl: Enabling PSR on SkylakeSonika Jindal
2015-01-27drm/i915/skl: Gen9 coarse power gatingZhe Wang
2015-01-27drm/i915: New offset for reading frequencies on CHV.Deepak S
2015-01-27drm/i915/chv: Populate total EU count on CherryviewDeepak S
2015-01-13drm/i915: Improve HiZ throughput on Cherryview.Kenneth Graunke
2015-01-12Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter
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