diff options
| author | Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> | 2015-03-05 19:33:08 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-17 22:30:13 +0100 |
| commit | 9cbe40c15a753e02f5da16f6de901decf3276cf1 (patch) | |
| tree | 3cec68ce0e5d71fc4778dcfc83d934bbaabce995 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | de3a0fde9afe551440db486f3f5ee52c8f15120a (diff) | |
drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
v2: Split the original changes into multiple smaller patches based on
review by Ville
v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.
v4: TDC target cnt is 10 bits and not 8 bits (Ville)
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4c64f17f188d..5f9a91f8fbc7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1041,6 +1041,8 @@ enum skl_disp_power_wells { #define _CHV_PLL_DW8_CH0 0x8020 #define _CHV_PLL_DW8_CH1 0x81A0 +#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 +#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) #define _CHV_PLL_DW9_CH0 0x8024 |