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2014-10-01drm/i915: Extract intel_runtime_pm.cDaniel Vetter
Geez is the audio hack ugly. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> [danvet: Rebased on top of the skl patches.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-10-01drm/i915: Remove intel_modeset_suspend_hwDaniel Vetter
Another layer of indirection for just an lpt-only w/a is a bit excessive. Reduce it. This was added in commit 7d708ee40a6b9ca1112a322e554c887df105b025 Author: Imre Deak <imre.deak@intel.com> Date: Wed Apr 17 14:04:50 2013 +0300 drm/i915: HSW: allow PCH clock gating for suspend Cc: Imre Deak <imre.deak@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-10-01drm/i915: spelling fixes for frontbuffer tracking kerneldocDaniel Vetter
Oh well. v2: Fix one more spelling fail Paulo spotted. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-10-01drm/i915: Tighting frontbuffer tracking around flipsDaniel Vetter
So I think I've spotted a small gap in the frontbuffer tracking while discussing the logic with Paulo on irc: 1. Userspace schedules gpu rendering to the current frontbuffer. This gets tracked in dev_priv->fb_tracking.busy_bits. 2. We pageflip a fully rendered buffer before the frontbuffer rendering completes. 3. The request retiring will never clear busy_bits (since at retire time the old frontbuffer won't have obj->frontbuffer_bits set), so these bits now are stuck until someone again does a bit of frontbuffer tracking. If we clear stale busy_bits in flip_prepare this gap is closed. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-30Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter
SKL stage 1 patches still need polish so will likely miss the 3.18 merge window. We've decided to postpone to 3.19 so let's pull this in to make patch merging and conflict handling easier. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-09-30drm/i915: preserve other DP_TEST_SINK bits.Rodrigo Vivi
Sink crc was implemented based on dp 1.1 spec that had all TEST_SINK bits reserved reading all 0s. But when reviewing my latest changes on sink crc Todd warned me that on new specs we have other valid bits on this reg that we might want to preserve. Cc: Todd Previte <tprevite@gmail.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Todd Previte <tprevite@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-30drm/i915/bdw: WaDisableFenceDestinationToSLMRodrigo Vivi
This WA affect BDW GT3 pre-production steppings. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Don't mention steppings ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-30drm/i915: Add IS_BDW_GT3 macro.Rodrigo Vivi
It will be usefull to specify w/a that affects only BDW GT3. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-30drm/i915: Fix Sink CRCRodrigo Vivi
In some cases like when PSR just got enabled the panel need more vblank times to calculate CRC. I figured that out with the new PSR test cases facing some cases that I had a green screen but a blank CRC. Even with 2 vblank waits on kernel + 2 vblank waits on test case. So let's give up to 6 vblank wait time. However we now check for TEST_CRC_COUNT that shows when panel finished to calculate CRC and has it ready. v2: Jani pointed out attempts decrements was wrong and should never reach the error condition. And Daniel pointed out that EIO is more appropriated than EGAIN. Also I realized that I have to read test_crc_count after setting test_sink v3: Rebase and adding error message Cc: Todd Previte <tprevite@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Todd Previte <tprevite@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-29drm/i915: Broadwell DDI Buffer translation - more tuningRodrigo Vivi
BDW display - DP buffer translation values changed to give better margin. Further change to entry 6; set dword 0 bit 31=1. Both changes were approved already but this one didn't landed BSpec yet this is why it is in a separated patch. Making reviewer's life easier. Also alowing separated tests and any future bisect that might be needed. Reference: Predator r74080 / HSD 4394389 v2: Arthur noticed I was changing the wrong bit. Cc: Arthur Runyan <arthur.j.runyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Arthur Runyan <arthur.j.runyan@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-29drm/i915: Broadwell DDI Buffer translation changed to give better margin.Rodrigo Vivi
Reference: Predator r73977 / HSD 4394389 Cc: Arthur Runyan <arthur.j.runyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Arthur Runyan <arthur.j.runyan@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-29drm/i915: Make sure PSR is ready for been re-enabled.Rodrigo Vivi
Let's make sure PSR is propperly disabled before to re-enabled it. According to Spec, after disabled PSR CTL, the Idle state might occur up to 24ms, that is one full frame time (1/refresh rate), plus SRD exit training time (max of 6ms), plus SRD aux channel handshake (max of 1.5ms). So if something went wrong PSR will be disabled until next full enable/disable setup. v2: The 24ms above takes in account 16ms for refresh rate on 60Hz mode. However on low frequency modes this can take longer. So let's use 50ms for safeness. v3: Move wait out of psr.lock critical area. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-29drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.Rodrigo Vivi
The sw cache clean on BDW is a tempoorary workaround because we cannot set cache clean on blt ring with risk of hungs. So we are doing the cache clean on sw. However we are doing much more than needed. Not only when using blt ring. So, with this extra w/a we minimize the ammount of cache cleans and call it only on same cases that it was being called on gen7. The traditional FBC Cache clean happens over LRI on BLT ring when there is a frontbuffer touch happening. frontbuffer tracking set fbc_dirty variable to let BLT flush that it must clean FBC cache. fbc.need_sw_cache_clean works in the opposite information direction of ring->fbc_dirty telling software on frontbuffer tracking to perform the cache clean on sw side. v2: Clean it a little bit and fully check for Broadwell instead of gen8. v3: Rebase after frontbuffer organization. v4: Wiggle confused me. So fixing v3! Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915: Avoid re-configure panel on every PSR re-enable.Rodrigo Vivi
The panel has to be reconfigured only when it really loose the power. The traditional enable/disable sequence already take care of this so we can minimize the time spend on every re-enable. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau
Gen9 is different enough (for instance, fetching the memory latency values is different from ILK+) to not take the HAS_PCH_SPLIT() branch, so let's prefer a clean separation. v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Introduce intel_num_planes()Damien Lespiau
It can be handy to get the number of planes for this pipe, ie including the primary plane to loop over them. Introduce a little function to do so. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Introduce a I915_MAX_PLANES macroDamien Lespiau
This can be useful to declare structures around pipes and planes and don't have to go back auditing the code if the next platorm bump that number. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Adjust assert_sprites_disabled()Damien Lespiau
Let's put to good use the new PLANE_CTL macros. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement drm_plane vfuncsDamien Lespiau
SKL Uses the same hardware for all planes now, so called "universal" planes. Ie both the primary planes and sprite planes share the same logic. This patch implements the drm_plane vfuncs for "sprites" ie planes that aren't the primary plane. v2: Couple of fixes: - Actually enabled the planes and fix the plane number Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Skylake has 2 "sprite" planes per pipeDamien Lespiau
On Skylake, we use plane1 as primary plane and plane2/3 as sprite planes. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Sunrise Point PCH detectionSatheeshakrishna M
This patch implements detection of SPT and SPT-LP PCH devices. v2: Added HAS_PCH_SPT macro Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Adjust the display engine interruptsDamien Lespiau
To accomodate the extra planes, the bit definitions were shuffled around a bit. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. v3: Rebase after yet another change int that area (done with wiggle) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M
Extending BDW implementation to gen9. Pipe B/C interrupt restoration after exiting LPSP. v2: Fix minor rebasing conflict. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL backlight enablingSatheeshakrishna M
Extending the BDW backlight implementation to SKL. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: vfuncs for skl eld and global resourceSatheeshakrishna M
Set gen 9 function pointers for eld write and global resource. Implementation remains same as HSW. v2: Rebase on top of Sonika's untangling of the if/else ladder (Damien) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL pipe misc programmingSatheeshakrishna M
Pipe misc programming in gen9 is similar to BDW. Extending the BDW implementation to gen 9. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL shares the same underrun interrupt as BDWDamien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Report the PDP regs as in gen8Damien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: report the same INSTDONE registers as gen8Damien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Allow the reg_read ioctl to return RCS_TIMESTAMPDamien Lespiau
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Initialize PPGTT like gen8Damien Lespiau
gen9 uses very similar memory management to what gen8 has. Just follow the flow. v2: Fix trivial conflict (Damien) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylakeDamien Lespiau
Skylake doesn't use the pre-charge field now, but, instead, we need to specify the total number of SYNC pulses for the SYNC phase (pre-charge + SYNC pattern pules). Let's use the default value (32) for that. v3: increase DP AUX TX timeout as 400us is not to be used on SKL apparently (Jesse). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement the get_aux_clock_divider() DP vfuncDamien Lespiau
We need to provide a vfunc that will make the code in intel_dp_aux_ch() loop once to start the AUX transaction. The return value (clock divider) is unused on SKL, so just return 1. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: gen9 uses the same bind_vma() vfuncs as gen6+Damien Lespiau
Temporary plug a BUG() while waiting for a better solution. See: http://lists.freedesktop.org/archives/intel-gfx/2014-January/038132.html However Chris was looking at cleaning-up this as well, so went for the easy intermediate solution instead. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add the additional graphics stolen sizesDamien Lespiau
Skylake introduces new stolen memory sizes starting at 0xf0 (4MB) and growing by 4MB increments from there. v2: Rebase on top of the early-quirk changes from Ville. v3: Rebase on top of the PCI_IDS/IDS macro rename Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Skylake moves AUX_CTL from PCH to CPUDamien Lespiau
So we can apply the old aux_ctl = dp_ctl + 0x10 rule again. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add support for DP voltage swings and pre-emphasisDamien Lespiau
They are similar to Haswell. v2: Rebased on top of drm-intel-nightly v3: Rebased on top of Sonika's DP train defines renaming Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Program the DDI buffer translation tablesDamien Lespiau
A couple of things have changed compared to Broadwell: - Entry 9 is used for eDP - No more FDI v2: Update the translation values to latest specs. v3: Rebase on top of the BDW HDMI translation patch v4: Remove the low voltage edp tables, Rebase on top of the patch not writing the HDMI entry on eDP/FDI DDIs (Satheesh, Paulo). v5: Apply the / 2 fix for the number of HDMI entries (Satheesh) v6: Rebase on top of Jani's clean up for the DDI_BUF_TRANS tables v7: Restore the commit message that was mangled by error Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Don't try to read out the PCH transcoder state if not presentDamien Lespiau
When the platform doesn't have a FDI link, don't try to read out the state of a potential PCH transcoder. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Don't open-code HAS_FDI if there's only one place that needs it. Acked by Damien on irc.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Don't create a VGA connector on SkylakeDamien Lespiau
v2: Rebase on top of the intel_crt_present() addition v3: Fix rebase error (we were patching the wrong function) Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement the new update_plane() for primary planesDamien Lespiau
Skylake makes primary planes the same as sprite planes and call the result "universal planes". This commit emulates a primary plane with plane 0, taking the opportunity to redefine primary and sprite registers to be identical now that the underlying hardware is. It also makes sense as plenty of fields have changed. v2: Rebase on top of the vma code. v3: Follow upstream evolution: - Drop return values. - Remove pipe checks since redudant and BUG instead. - Remove tiling checks and BUG instead. - Drop commented out DISP_MODIFY usage. v4: s/plane/primary_plane/ v5: Misc fixes: - Fix the fields we need to clear up - Disable trickle feed - Correctly use PLANE_OFFSET for the panning v6: (Jesse) Use pipe src size when programming plane size. This makes cloned configs work correctly w/o the use of a panel fitter. v7: Rebase on top of Ville's rmw elimination series v8: Remove clearing the trickle feed bit now that we don't do a RMW (Rodrigo, Damien) Add a comment about the stride unit (Rodrigo) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1,5,6,7) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2,3) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: i915_swizzle_info gen9 fixRobert Beckett
Fix ARB_MODE register read for gen >= 8 in i915_swizzle_info Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Robert Beckett <robert.beckett@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-24drm/i915/skl: Framebuffers need to be aligned to 256KB on SkylakeDamien Lespiau
v2: Also align X tiled fbs to 256KB (Thomas) Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+Imre Deak
The following sets the AsyncFlip performance mode for everything above Gen6: commit 4790cb36b3eede8fb0cca529dc1d31b9936fa24b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sun Jan 20 16:11:20 2013 +0000 drm/i915: Disable AsyncFlip performance optimisations Starting from Gen9 the MI_MODE register layout changes and doesn't include the above bit. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Skylake shares the interrupt logic with BroadwellDamien Lespiau
Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Provide a placeholder for init_clock_gating()Damien Lespiau
v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Fence registers on SKL are the same as SNBDamien Lespiau
v2: Rebased on top of the i915_gpu_error.c extraction. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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