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authorSean Paul <seanpaul@chromium.org>2014-10-01 12:40:41 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2015-02-02 15:46:34 +0200
commitf892f24b37345181b9bc7748ed4a8e927cdb6e06 (patch)
tree75c2f3ba5b9dde77bc4487dad5ad24f8bc2e941b /drivers/clk/clk-moxart.c
parent18abd16376ad88ed3995c63ddae47be78bd56abe (diff)
clk: tegra124: Add init data for dsi lp clocks
Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/clk-moxart.c')
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