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authorAndrew Bresticker <abrestic@chromium.org>2014-11-06 14:47:55 -0800
committerPeter De Schrijver <pdeschrijver@nvidia.com>2015-02-02 15:46:14 +0200
commit18abd16376ad88ed3995c63ddae47be78bd56abe (patch)
tree149e4b0e10e149d65d4cef3f0f9a0c6f76a17394 /drivers/clk/clk-moxart.c
parente36f014edff70fc02b3d3d79cead1d58f289332e (diff)
clk: tegra: SDMMC controllers are on APB
Since the SDMMC controller registers are accessed via the APB, the APB must be flushed before gating the SDMMC clocks to prevent register accesses to the SDMMC controllers after their clocks are gated. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/clk-moxart.c')
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