diff options
author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:46 +0200 |
---|---|---|
committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:24:01 +0200 |
commit | 142439b0520a239bc10cf6c87d7773644c5dfe04 (patch) | |
tree | d5b96654d4cf4f3895a0f75d048f06944e20cb10 /arch/mips/include/asm/mach-sibyte | |
parent | 44def3426e4ac5a2dbdb5c8304397f4daa38eb2f (diff) |
MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-sibyte')
-rw-r--r-- | arch/mips/include/asm/mach-sibyte/war.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index 78fd2ad4930b..0e18f0753407 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -24,8 +24,6 @@ extern int sb1250_m3_workaround_needed(void); #endif -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0 #define ICACHE_REFILLS_WORKAROUND_WAR 0 #define R10000_LLSC_WAR 0 |