diff options
| author | Duc Dang <dhdang@apm.com> | 2015-10-22 18:54:57 -0700 |
|---|---|---|
| committer | Duc Dang <dhdang@apm.com> | 2015-11-17 13:11:53 -0800 |
| commit | b0e7a85a97413fb47f6ba40ac5497cfa40758664 (patch) | |
| tree | 019244f71eb32520002303585cb2ac0eceed1e9f /arch/arm64/boot/dts/apm | |
| parent | 0ae8c000210ffe1a4ac93ad1bc4a8cce11841553 (diff) | |
arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block
Remove register information used to reset and enable/disable clock
for AHB block as reseting AHB or disabling its clock will make other
peripherals attached to it stop working.
Signed-off-by: Duc Dang <dhdang@apm.com>
Diffstat (limited to 'arch/arm64/boot/dts/apm')
| -rw-r--r-- | arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/apm/apm-storm.dtsi | 11 |
2 files changed, 6 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 718ffc431b19..ddf1e86fa67e 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -140,17 +140,12 @@ clock-output-names = "socplldiv2"; }; - ahbclk: ahbclk@1f2ac000 { + ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x1>; - enable-offset = <0x8>; - enable-mask = <0x1>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "div-reg"; divider-offset = <0x164>; divider-width = <0x5>; divider-shift = <0x0>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 445f68d83051..32f9ba9b6962 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -150,17 +150,12 @@ clock-output-names = "socplldiv2"; }; - ahbclk: ahbclk@1f2ac000 { + ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x1>; - enable-offset = <0x8>; - enable-mask = <0x1>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "div-reg"; divider-offset = <0x164>; divider-width = <0x5>; divider-shift = <0x0>; |