diff options
| author | Duc Dang <dhdang@apm.com> | 2015-09-16 17:12:57 +0530 |
|---|---|---|
| committer | Duc Dang <dhdang@apm.com> | 2015-11-17 13:11:53 -0800 |
| commit | 0ae8c000210ffe1a4ac93ad1bc4a8cce11841553 (patch) | |
| tree | a9dd9e123d78d5859475788c214fb14b820dce54 /arch/arm64/boot/dts/apm | |
| parent | 8f74e861862e17b3f03f095f6b3e8dc3bddc5f0c (diff) | |
arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene v2 SoC platforms.
Signed-off-by: Duc Dang <dhdang@apm.com>
Diffstat (limited to 'arch/arm64/boot/dts/apm')
| -rw-r--r-- | arch/arm64/boot/dts/apm/apm-merlin.dts | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 44 |
2 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 119a469bd189..a0092f977591 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -70,3 +70,7 @@ &xgenet1 { status = "ok"; }; + +&mmc0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c804f8f1f38c..718ffc431b19 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -140,6 +140,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + pcie0clk: pcie0clk@1f2bc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -224,6 +258,16 @@ dma-coherent; }; + mmc0: mmc@1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + no-1-8-v; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; |