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authorAnup Patel <anup.patel@wdc.com>2020-06-01 14:45:40 +0530
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-06-09 19:11:21 -0700
commit6b7ce8927b5a4d739670d4dc0de301f2abfd9a5c (patch)
tree114283592a0541d13736f2f77cd8df5004d48df3 /Documentation/filesystems/api-summary.rst
parentd175d699df07041befda3779f29bf7126c298730 (diff)
irqchip: RISC-V per-HART local interrupt controller driver
The RISC-V per-HART local interrupt controller manages software interrupts, timer interrupts, external interrupts (which are routed via the platform level interrupt controller) and other per-HART local interrupts. We add a driver for the RISC-V local interrupt controller, which eventually replaces the RISC-V architecture code, allowing for a better split between arch code and drivers. The driver is compliant with RISC-V Hart-Level Interrupt Controller DT bindings located at: Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt Co-developed-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> [Palmer: Cleaned up warnings] Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
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