blob: 139cf8538645c7bd7e099c0737f689069c151aac (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
# SPDX-License-Identifier: MIT
CONFIG_SOC_SERIES_STM32F0X=y
CONFIG_SOC_STM32F072XB=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# Floating Point Options
CONFIG_FPU=y
# enable GPIO
CONFIG_GPIO=y
# Needed to reduce this to size that will fit on F072
CONFIG_HEAP_MEM_POOL_SIZE=1024
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSI as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=12
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
|
