diff options
author | Nick <nick.win999@gmail.com> | 2020-08-02 10:29:07 -0500 |
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committer | Nick <nick.win999@gmail.com> | 2020-08-02 10:29:07 -0500 |
commit | bc282a0a4f1af4f6f78a0dd63e5b022eb76a603c (patch) | |
tree | 3b65b05e84d864964922d2a97e0b79438c2cda62 /app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig | |
parent | 2ba4385f4954a1bec9b080a35c15a4311d7cb28e (diff) |
WIP DZ60RGB board definition
Diffstat (limited to 'app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig')
-rw-r--r-- | app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig b/app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig new file mode 100644 index 0000000..5a4c099 --- /dev/null +++ b/app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: MIT + +CONFIG_SOC_SERIES_STM32F3X=y +CONFIG_SOC_STM32F303XC=y +# 72MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 + +# enable pinmux +CONFIG_PINMUX=y + +# enable GPIO +CONFIG_GPIO=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# Clock configuration for Cube Clock control driver +CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 +CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y +# use HSE as PLL input +CONFIG_CLOCK_STM32_PLL_SRC_HSE=y +# however, the board does not have an external oscillator, so just use +# the 8MHz clock signal coming from integrated STLink +CONFIG_CLOCK_STM32_HSE_BYPASS=y +# produce 72MHz clock at PLL output +CONFIG_CLOCK_STM32_PLL_PREDIV=1 +CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9 +CONFIG_CLOCK_STM32_AHB_PRESCALER=1 +CONFIG_CLOCK_STM32_APB1_PRESCALER=2 +CONFIG_CLOCK_STM32_APB2_PRESCALER=1 |