summaryrefslogtreecommitdiff
path: root/firmware/target/arm/mmu-arm.S
AgeCommit message (Collapse)Author
2012-06-07imx233: define HAVE_TEST_AND_CLEAN_CACHEAmaury Pouly
Change-Id: I7ceb9b122520e48a88f6299f10d42d2fa717ef3b
2011-12-17Commit to certain names for cache coherency APIs and discard the aliases.Michael Sevakis
Wouldn't surprise me a bit to get some non-green. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657
2011-12-17Do some things to make -ffunction-sections work better.Michael Sevakis
* Add wildcards to various sections placements a la *(".text") => "*(.text*)" * Remove hacky bits from those linker scripts (no problem encountered testing) * Change section for asm functions from .<section> to .<section>.<function> so that -ffunction-sections works for those asm file too. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31337 a1c6a512-1295-4272-9138-f99709370657
2011-07-23imx233/fuze+: prepare target to enable MMUAmaury Pouly
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30199 a1c6a512-1295-4272-9138-f99709370657
2011-01-02New port: iPod Classic (also known as iPod 6G/6.5G/7G)Michael Sparmann
Major known issues: - No bootloader yet - No support for the first-generation 160GB CE-ATA hard disk drive yet - Audio playback is slow, only FLAC seems to reach realtime git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28953 a1c6a512-1295-4272-9138-f99709370657
2010-09-08Rename cache coherency functions.Thomas Martitz
The old cache coherency function names where wrong and misleading. The new names are (purposely different from vendor manuals) * commit_* (write-back only) * discard_* (removing lines from cache only) * commit_discard_* (write-back and removing lines from cache) It's suspected the old names have led to wrong uses. The old names still exist (as aliases) so every call via the old names need to be double checked and changed to the new name. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
2010-05-30Update Samsung YP-S3 bootloader demoBertrik Sikken
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26417 a1c6a512-1295-4272-9138-f99709370657
2010-05-29cpucache_invalidate: use bx reg instead of mov pc, reg to returnRafaël Carré
Using BX has the effect to set the T bit, so it can return to a thumb function With this change, rockbox runs fine on Clipv2 built with -mthumb (for most files which don't use inline 32 bits ARM assembly) Some other places use code which change the T bit on armv5 but not on armv4 so armv4 won't run See FS#6734 git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26386 a1c6a512-1295-4272-9138-f99709370657
2010-05-13as3525: use DMA for recordingRafaël Carré
Flyspray: FS#11257 git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25980 a1c6a512-1295-4272-9138-f99709370657
2010-04-13s5l870x : use mmu-arm.SRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25634 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm.S: comment out dump_dcache_range()Rafaël Carré
It is only used by gigabeats, and is defined in mmu-armv6.S already git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25630 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm.S: disable MMU functions on CPUs which don't use themRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25629 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm.S: Use correct implementations on arm926ej-s CPUsRafaël Carré
clean_dcache and invalidate_dcache were incorrect and too tied to the arm920t/arm922t 64-way set associative caches Make those functions smaller on as3525, as this CPU has a smaller cache than the gigabeat F/X Flyspray: FS#11106 Authors: Jack Halpin and myself git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25628 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm* : cpucache_invalidate() needs to be in IRAM for roloRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25627 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm (v4/v5) : fix previous commit, clean/invalidate correctly the first ↵Rafaël Carré
segment in each loop git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25626 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm (v4/v5) : use one less instruction in invalidate_dcache/clean_dcacheRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25625 a1c6a512-1295-4272-9138-f99709370657
2009-10-18Split ARMv6 code from mmu-arm.SRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23244 a1c6a512-1295-4272-9138-f99709370657
2009-10-17Fix S5L870x cache coherency functions. They were split into a different ↵Michael Sparmann
file, as changes were needed all over the place. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23239 a1c6a512-1295-4272-9138-f99709370657
2009-10-09Added S5L870X cache coherency supportMichael Sparmann
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23058 a1c6a512-1295-4272-9138-f99709370657
2009-02-11Refine the routines in mmu-arm.c and move them to mmu-arm.S since the code ↵Michael Sevakis
is now 100% assembly. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19980 a1c6a512-1295-4272-9138-f99709370657
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 22:29:25 +0000