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path: root/firmware/target/arm/mmu-arm.S
AgeCommit message (Collapse)Author
2010-05-30Update Samsung YP-S3 bootloader demoBertrik Sikken
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26417 a1c6a512-1295-4272-9138-f99709370657
2010-05-29cpucache_invalidate: use bx reg instead of mov pc, reg to returnRafaël Carré
Using BX has the effect to set the T bit, so it can return to a thumb function With this change, rockbox runs fine on Clipv2 built with -mthumb (for most files which don't use inline 32 bits ARM assembly) Some other places use code which change the T bit on armv5 but not on armv4 so armv4 won't run See FS#6734 git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26386 a1c6a512-1295-4272-9138-f99709370657
2010-05-13as3525: use DMA for recordingRafaël Carré
Flyspray: FS#11257 git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25980 a1c6a512-1295-4272-9138-f99709370657
2010-04-13s5l870x : use mmu-arm.SRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25634 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm.S: comment out dump_dcache_range()Rafaël Carré
It is only used by gigabeats, and is defined in mmu-armv6.S already git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25630 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm.S: disable MMU functions on CPUs which don't use themRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25629 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm.S: Use correct implementations on arm926ej-s CPUsRafaël Carré
clean_dcache and invalidate_dcache were incorrect and too tied to the arm920t/arm922t 64-way set associative caches Make those functions smaller on as3525, as this CPU has a smaller cache than the gigabeat F/X Flyspray: FS#11106 Authors: Jack Halpin and myself git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25628 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm* : cpucache_invalidate() needs to be in IRAM for roloRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25627 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm (v4/v5) : fix previous commit, clean/invalidate correctly the first ↵Rafaël Carré
segment in each loop git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25626 a1c6a512-1295-4272-9138-f99709370657
2010-04-13mmu-arm (v4/v5) : use one less instruction in invalidate_dcache/clean_dcacheRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25625 a1c6a512-1295-4272-9138-f99709370657
2009-10-18Split ARMv6 code from mmu-arm.SRafaël Carré
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23244 a1c6a512-1295-4272-9138-f99709370657
2009-10-17Fix S5L870x cache coherency functions. They were split into a different ↵Michael Sparmann
file, as changes were needed all over the place. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23239 a1c6a512-1295-4272-9138-f99709370657
2009-10-09Added S5L870X cache coherency supportMichael Sparmann
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23058 a1c6a512-1295-4272-9138-f99709370657
2009-02-11Refine the routines in mmu-arm.c and move them to mmu-arm.S since the code ↵Michael Sevakis
is now 100% assembly. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19980 a1c6a512-1295-4272-9138-f99709370657
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