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path: root/firmware/target/arm/imx31/dvfs_dptc-imx31.c
AgeCommit message (Collapse)Author
2013-05-11i.MX31: Remove long udelay from DVFS interrupt handlerMichael Sevakis
Split the ISR into two parts and alllow quick return from first half. Introduces a uevent() API to have a callback happen in a specified number of microseconds. Right now only one event is supported. Change-Id: Ib1666165be2f6082e5275d64961f083cab104f9f
2011-12-09Introduce USED_ATTR wrapper for __attribute__((used)).Boris Gjenero
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31188 a1c6a512-1295-4272-9138-f99709370657
2011-10-14i.MX31: Simplify nested interrupt handling. Give SVC mode its own stack by ↵Michael Sevakis
grabbing the FIQ stack that's just been taking up space. Just get rid of all FIQ setup since it isn't used anyway. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30747 a1c6a512-1295-4272-9138-f99709370657
2011-01-23i.MX31: Now that it matters because there's a debug screeen that allows ↵Michael Sevakis
changing things while running, some DVFS/DPTC stuff has to be done more carefully. Trim out some stuff and group functions better as well. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29122 a1c6a512-1295-4272-9138-f99709370657
2011-01-22Fix yellow. Left an unused temp variable.Michael Sevakis
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29117 a1c6a512-1295-4272-9138-f99709370657
2011-01-22i.MX31: Allow interrupts in thread context, not just ISR context, during the ↵Michael Sevakis
lengthy DVFS voltage ramp-up delay. Also, explicitly enable them just before mc13783_init since that does anyway because of the PMIC write inside it. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29116 a1c6a512-1295-4272-9138-f99709370657
2011-01-22i.MX31: Add a debug menu to play around with DVFS/DPTC settings for fun, ↵Michael Sevakis
testing or benchmarking purposes. Can set the CPU frequency working point, whether DPTC voltage scaling is enabled and change the software-programmable load tracking weights. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29113 a1c6a512-1295-4272-9138-f99709370657
2011-01-07Gigabeat S/i.MX31: Take care of an interrupt priority inversion that can ↵Michael Sevakis
happen during PCM callback lockout when DVFS switches frequecies during the lockout, preventing a thread from unlocking the callback until DVFS finishes, causing an SSI FIFO underrun. Hadn't thought of an acceptable way to deal with it before. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28996 a1c6a512-1295-4272-9138-f99709370657
2010-06-30Remove atomic register bit manipulation functions from i.MX and s3c target ↵Michael Sevakis
code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657
2010-06-11Configure Gigabeat S with EABI compiler by default. Implement the INIT ↵Michael Sevakis
section that this enables (due to selective need for long calls). Remove pcm_postinit from INIT section since it's asynchronous. Disable strict aliasing on SPC codec for now just to shut it up. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26779 a1c6a512-1295-4272-9138-f99709370657
2010-05-06Gigabeat S bootloader: Fix archaic call placement in dptc_stop which hangs ↵Michael Sevakis
the bootloader before jumping to FW. Let the backlight LED ramp up after unplugging USB which just looks better. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25840 a1c6a512-1295-4272-9138-f99709370657
2010-05-06i.MX31/Gigabeat S: This should fix stability problems. One problem was to ↵Michael Sevakis
start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657
2010-05-05i.MX31/Gigabeat S: The nested IRQ code was just totally wrong and not ↵Michael Sevakis
actually working anyway (which is why it wasn't crashing). AVIC doesn't seem truthful about priority of current ISR either :\. Sometimes there were channel swaps during really active DVFS due to FIFO underflow from a needed long delay in the ISR (100us, and IIS TX only has 45us reserve) and DMARQ *must* be serviced low-latency. Get it doing as was intended. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25822 a1c6a512-1295-4272-9138-f99709370657
2010-05-04Merely correct a comment.Michael Sevakis
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25802 a1c6a512-1295-4272-9138-f99709370657
2010-05-04i.MX31/Gigabeat S: Just a little paranoid change to switcher write to active ↵Michael Sevakis
regulators method, to keep things localized a bit more from global data pool, for safety's sake. It's going to Mars afterall. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25801 a1c6a512-1295-4272-9138-f99709370657
2010-05-04i.MX31/Gigabeat S: Actually enable DPTC which can set optimal voltage for ↵Michael Sevakis
528MHz. Requires an SPI and PMIC interface rework because of the low-latency needs for the DPTC to work best with minimal panicing. SPI can work with multitasking and asynchronously from interrupt handlers or normal code. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25800 a1c6a512-1295-4272-9138-f99709370657
2010-04-23i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for ↵Michael Sevakis
528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
2010-04-07Gigabeat S (imx31): Begin voltage and frequency scaling code. For now, to ↵Michael Sevakis
avoid overdrive voltage, just lower core voltage to 1.35V since voltage scaling shouldn't be required for frequencies lower than 399 MHz (according to Freescale BSP, which set all working points to 1.35V for those frequencies). Perhaps battery life will improve as well (cross fingers :). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25506 a1c6a512-1295-4272-9138-f99709370657
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