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-rw-r--r--firmware/target/coldfire/iaudio/m3/adc-m3.c17
1 files changed, 14 insertions, 3 deletions
diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c
index b0d7f7430b..1f17b1e3f1 100644
--- a/firmware/target/coldfire/iaudio/m3/adc-m3.c
+++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c
@@ -51,8 +51,8 @@ void IIC2(void)
MBSR2 &= ~IFF; /* Clear interrupt flag */
- if (MBSR2 & IAL) /* Arbitration lost - shouldn't happen */
- { /* normally, but CPU freq change might induce it */
+ if (MBSR2 & IAL) /* Arbitration lost - shouldn't never happen */
+ {
MBSR2 &= ~IAL; /* Clear flag */
MBCR2 &= ~MSTA; /* STOP */
}
@@ -97,7 +97,6 @@ void adc_init(void)
MBSR2 = 0; /* Clear flags */
MBCR2 = (IEN|IIEN); /* Enable interrupts */
- and_l(~0x0f000000, &INTPRI8);
or_l( 0x04000000, &INTPRI8); /* INT62 - Priority 4 */
tick_add_task(adc_tick);
@@ -105,3 +104,15 @@ void adc_init(void)
while (!data_ready)
sleep(1); /* Ensure valid readings when adc_init returns */
}
+
+/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C
+ * implementation. If a transfer is stopped prematurely, it often locks up
+ * and doesn't react anymore until the unit is power cycled. */
+
+void adc_close(void)
+{
+ tick_remove_task(adc_tick);
+
+ while (MBSR2 & IBB) /* Wait for an ongoing transfer to finish */
+ sleep(1);
+}