diff options
| author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 08:22:52 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 11:42:45 -0400 |
| commit | 62146ed73513ec62b57163d229c6719b9349c640 (patch) | |
| tree | 3e4cb2585216e98bd07cc05e7683804f3d1e369b /firmware | |
| parent | 89c7a4e3935ddb61861a208897f0db81f1cd5ecb (diff) | |
jz4760: Fixes in PLL calculation and reporting
Change-Id: I890c661fbff549de5a224d90e3fbda34c71b3a7e
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/codec-jz4760.c | 2 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/debug-jz4760.c | 2 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 22 |
3 files changed, 12 insertions, 14 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c index 7e210e21f9..95628841dc 100644 --- a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c @@ -197,7 +197,7 @@ void pll1_disable(void); void audiohw_set_frequency(int fsel) { unsigned int pll1_speed; - unsigned char mclk_div, bclk_div, func_mode; + unsigned short mclk_div, bclk_div, func_mode; // bclk is 1..8 // mclk is 1..512 diff --git a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c index 92421b2c1e..ee247a9cff 100644 --- a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c @@ -42,7 +42,7 @@ static void display_clocks(void) unsigned int cppcr0 = REG_CPM_CPPCR0; /* PLL Control Register */ unsigned int cppcr1 = REG_CPM_CPPCR1; /* PLL Control Register */ unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - unsigned int od[4] = {1, 2, 2, 4}; + unsigned int od[4] = {1, 2, 4, 8}; lcd_putsf(0, line++, "CPPCR0:0x%08x", cppcr0); if (cppcr0 & CPPCR0_PLLEN) { diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index 072bdb49b8..73e9ab7749 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c @@ -362,18 +362,18 @@ static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal const int pll_m_max = 0x7f, pll_m_min = 4; const int pll_n_max = 0x0f, pll_n_min = 2; - int od[] = {1, 2, 4, 8}; + unsigned char od[] = {1, 2, 4, 8}; unsigned int plcr_m_n_od = 0; unsigned int distance; - unsigned int tmp, raw; + unsigned int tmp; int i, j, k; int m, n; distance = 0xFFFFFFFF; - for (i = 0; i < (int)sizeof (od) / (int)sizeof(int); i++) { + for (i = 0; i < (int)sizeof(od); i++) { /* Limit: 500MHZ <= CLK_OUT * OD <= 1500MHZ */ if ((speed * od[i]) < 500 * MHZ || (speed * od[i]) > 1500 * MHZ) continue; @@ -383,15 +383,13 @@ static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal /* Limit: 1MHZ <= XIN/N <= 50MHZ */ if ((xtal / n) < (1 * MHZ)) break; - if ((xtal / n) > (15 * MHZ)) + if ((xtal / n) > (50 * MHZ)) continue; for (j = pll_m_min; j <= pll_m_max; j++) { m = j*2; - raw = xtal * m / n; - tmp = raw / od[i]; - + tmp = xtal * m / (n * od[i]); tmp = (tmp > speed) ? (tmp - speed) : (speed - tmp); if (tmp < distance) { @@ -419,16 +417,16 @@ static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal static void pll0_init(unsigned int freq) { register unsigned int cfcr, plcr1; - int n2FR[9] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5 - }; + int usbdiv; /** divisors, * for jz4760b,I:H:H2:P:M:S. * DIV should be one of [1, 2, 3, 4, 6, 8] */ - int div[6] = {1, 4, 4, 4, 4, 4}; - int usbdiv; + const int div[6] = {1, 4, 4, 4, 4, 4}; + const int n2FR[9] = { + 0, 0, 1, 2, 3, 0, 4, 0, 5 + }; /* @ CPU_FREQ of 492MHZ, this means: 492MHz CCLK |