well there was a big bug (read more carefully the instruction descriptions) ;)

you can find why commented in the source

i'll fix it, but not test it


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@226 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 73 insertions, 1 deletions

diff --git a/firmware/thread.c b/firmware/thread.c
index e3116fbeb5..402f2123fe 100644
--- a/firmware/thread.c
+++ b/firmware/thread.c
@@ -25,7 +25,9 @@ typedef union
         unsigned int  r[7]; /* Registers r8 thru r14 */
         void          *sp;  /* Stack pointer (r15) */
         unsigned int  sr;   /* Status register */
+#if 0
         void*         gbr;  /* Global base register */
+#endif
         void*         pr;   /* Procedure register */
     } regs;
     unsigned int mem[32];
@@ -47,7 +49,33 @@ static thread_t threads = {1, 0};
 static inline void stctx(void* addr)
 {
     unsigned int tmp;
-    
+
+    /*
+      [Alkorr] sorry, this code is totally wrong.
+      
+      Why ?
+
+        "mov.l %0,@(imm,%1)"
+
+      must be interpreted as :
+      
+        "%0 = ((long *)%1)[imm]"  
+      
+      not as :
+      
+        "%0 = *((long *)(((char *)%1) + imm))"
+
+      real offset = "imm" x 1 if byte access (.b)
+                  = "imm" x 2 if 16-bit word access (.w)
+                  = "imm" x 4 if 32-bit word access (.l)
+
+      Don't forget, SH doesn't like misaligned address, so
+      remember it doesn't make any sense to have an odd
+      offset ;).
+
+    */
+
+#if 0
     asm volatile ("mov.l r8, @(0, %1)\n\t"
                   "mov.l r9, @(4, %1)\n\t"
                   "mov.l r10, @(8, %1)\n\t"
@@ -64,6 +92,34 @@ static inline void stctx(void* addr)
                   "mov.l %0, @(4, %1)\n\t"
                   "sts pr, %0\n\t"
                   "mov.l %0, @(8, %1)" : "=r&" (tmp) : "r" (addr));
+#endif
+#if 0
+    /* here the right code */
+    asm volatile ("mov.l r8,  @(0,%1)\n\t"
+                  "mov.l r9,  @(1,%1)\n\t"
+                  "mov.l r10, @(2,%1)\n\t"
+                  "mov.l r11, @(3,%1)\n\t"
+                  "mov.l r12, @(4,%1)\n\t"
+                  "mov.l r13, @(5,%1)\n\t"
+                  "mov.l r14, @(6,%1)\n\t"
+                  "mov.l r15, @(7,%1)\n\t"
+                  "stc.l sr,  %0\n\t"
+                  "mov.l %0,  @(8,%1)\n\t"
+                  "sts   pr,  %0\n\t"
+                  "mov.l %0,  @(9,%1)" : "=r&" (tmp) : "r" (addr));
+#endif
+    /* here a far better code */
+    asm volatile ("sts.l pr,  @-%0\n\t"
+                  "stc.l sr,  @-%0\n\t"
+                  "mov.l r15, @-%0\n\t"
+                  "mov.l r14, @-%0\n\t"
+                  "mov.l r13, @-%0\n\t"
+                  "mov.l r12, @-%0\n\t"
+                  "mov.l r11, @-%0\n\t"
+                  "mov.l r10, @-%0\n\t"
+                  "mov.l r9,  @-%0\n\t"
+                  "mov.l r8,  @-%0" : : "r" (addr+4*10));
+   
 }
 
 /*--------------------------------------------------------------------------- 
@@ -74,6 +130,9 @@ static inline void ldctx(void* addr)
 {
     unsigned int tmp;
     
+    /* same remarks than above */
+
+#if 0
     asm volatile ("mov.l @(0, %1), r8\n\t"
                   "mov.l @(4, %1), r9\n\t"
                   "mov.l @(8, %1), r10\n\t"
@@ -91,6 +150,19 @@ static inline void ldctx(void* addr)
                   "mov.l @(8, %1), %0\n\t"
                   "lds %0, pr\n\t"
                   "mov.l %0, @(0, r15)" : "=r&" (tmp) : "r" (addr));
+#endif
+    asm volatile ("mov.l @%0+,r8\n\t"
+                  "mov.l @%0+,r9\n\t"
+                  "mov.l @%0+,r10\n\t"
+                  "mov.l @%0+,r11\n\t"
+                  "mov.l @%0+,r12\n\t"
+                  "mov.l @%0+,r13\n\t"
+                  "mov.l @%0+,r14\n\t"
+                  "mov.l @%0+,r15\n\t"
+                  "lds.l @%0+,pr\n\t"
+                  "ldc.l @%0+,sr"
+                   : : "r" (addr));
+
 }
 
 /*---------------------------------------------------------------------------