diff options
| author | Jonathan Gordon <rockbox@jdgordon.info> | 2007-02-18 01:17:06 +0000 |
|---|---|---|
| committer | Jonathan Gordon <rockbox@jdgordon.info> | 2007-02-18 01:17:06 +0000 |
| commit | 1083de8e7dd9360c999dbfe08cdf5d7c1ee5c4a6 (patch) | |
| tree | 3d7684811452c44a4c499c35341a98bfb66fc814 /firmware/target/coldfire/iriver | |
| parent | c2f05592ee1ba8399b64b5f63669c0eaa8cb8e0e (diff) | |
CONFIG_USBOTG fixes
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12377 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iriver')
| -rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index 32fc44f963..1cb0a502be 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c @@ -85,7 +85,7 @@ void set_cpu_frequency(long frequency) PLLCR = 0x018ae025 | (PLLCR & 0x70400000); CSCR0 = 0x00001180; /* Flash: 4 wait states */ CSCR1 = 0x00001580; /* LCD: 5 wait states */ -#if CONFIG_USBOTG == USBOTG_ISP1362 +#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ #endif while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. @@ -112,7 +112,7 @@ void set_cpu_frequency(long frequency) PLLCR = 0x038be025 | (PLLCR & 0x70400000); CSCR0 = 0x00000580; /* Flash: 1 wait state */ CSCR1 = 0x00000180; /* LCD: 0 wait states */ -#if CONFIG_USBOTG == USBOTG_ISP1362 +#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ #endif while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. @@ -139,7 +139,7 @@ void set_cpu_frequency(long frequency) PLLCR = 0x00800200 | (PLLCR & 0x70400000); CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */ -#if CONFIG_USBOTG == USBOTG_ISP1362 +#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ #endif DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |