diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2010-05-11 14:09:26 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2010-05-11 14:09:26 +0000 |
| commit | 8261051b37871e7d64340643458fe0ca9d0fa19f (patch) | |
| tree | a2b46778d2d66c874f1efe40f44a6ce68dcfe1fd /firmware/target/arm | |
| parent | aaa07970eee7c9fcfa0964f45c856f96533686aa (diff) | |
Gigabeat F/X: Let us clear up confusion about just what the core frequency is. Fix frequency display in buffering screen.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25953 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
| -rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index 0721feeee4..ad32f89552 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h @@ -27,14 +27,16 @@ /* NB: These values must match the register settings in s3c2440/crt0.S */ #ifdef GIGABEAT_F - #define CPUFREQ_DEFAULT 98784000 - #define CPUFREQ_NORMAL 98784000 - #define CPUFREQ_MAX 296352000 + /* MPLLCON = 0x000C9042, 16.9344 MHz refclk, therefore: + * MPLL = 294940800 = 2*(201 + 8)*16934400 / ((4 + 2) * 2^2) */ + #define CPUFREQ_DEFAULT 98313600 + #define CPUFREQ_NORMAL 98313600 + #define CPUFREQ_MAX 294940800 /* Uses 1:3:6 */ #define FCLK CPUFREQ_MAX - #define HCLK (FCLK/3) /* = 98,784,000 */ - #define PCLK (HCLK/2) /* = 49,392,000 */ + #define HCLK (FCLK/3) /* = 98,313,600 */ + #define PCLK (HCLK/2) /* = 49,156,800 */ #ifdef BOOTLOADER /* All addresses within rockbox are in IRAM in the bootloader so |