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| author | Mihail Zenkov <mihail.zenkov@gmail.com> | 2016-03-27 21:06:27 +0000 |
|---|---|---|
| committer | Mihail Zenkov <mihail.zenkov@gmail.com> | 2016-03-27 21:06:27 +0000 |
| commit | 77a35363c59dabb0a0ead6b8c078d3de8dd0a248 (patch) | |
| tree | bbc00b9dc8b8cd3c0c85f79b7480f9bf1f131f95 /firmware/target/arm | |
| parent | ee567d8579030669e1fc39197a7579a32c65aa0a (diff) | |
AMSv2: DBOP frequency divided by 2
After setting new PCLK (96 Mhz) we have too high DBOP (96 / 16 = 6 MHz).
According to datasheet DBOP should be maximum 4 MHz.
Change-Id: I1cbec054f41a76a6f18eadccb902c5b174ad6e3a
Diffstat (limited to 'firmware/target/arm')
| -rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index f4bb5568fb..7f6b17eff4 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -86,6 +86,8 @@ #define AS3525_DRAM_FREQ 96000000 /* Initial DRAM frequency */ +#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ +#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/2) /* DBOP divided from PCLK freq */ #else /* AS3525v1 */ @@ -113,12 +115,11 @@ #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ #define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ +#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ +#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ #endif /* CONFIG_CPU == AS3525v2 */ -#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ - -#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ /** ****************************************************************************/ |