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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2008-05-17 14:20:09 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2008-05-17 14:20:09 +0000
commitaffa4f668e1e9bea785b5e2bb643b96b246b52ad (patch)
tree7d3891c3fdc9b243e01b328a3595fdfc1b3327dd /firmware/target/arm/tms320dm320
parentff78cd84185e44943feca14671b111339030809f (diff)
Use OF's firmware loading mechanism instead of Rockbox's.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17553 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320')
-rw-r--r--firmware/target/arm/tms320dm320/app.lds8
-rwxr-xr-xfirmware/target/arm/tms320dm320/crt0.S4
2 files changed, 12 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/app.lds b/firmware/target/arm/tms320dm320/app.lds
index 64610a3577..0a9aa85bc4 100644
--- a/firmware/target/arm/tms320dm320/app.lds
+++ b/firmware/target/arm/tms320dm320/app.lds
@@ -81,9 +81,13 @@ SECTIONS
_vectorsstart = .;
*(.vectors);
_vectorsend = .;
+#ifndef CREATIVE_ZVx
} > IRAM AT> DRAM
_vectorscopy = LOADADDR(.vectors);
+#else
+ } > IRAM
+#endif
.iram :
{
@@ -93,9 +97,13 @@ SECTIONS
*(.idata)
. = ALIGN(0x4);
_iramend = .;
+#ifndef CREATIVE_ZVx
} > IRAM AT> DRAM
_iramcopy = LOADADDR(.iram);
+#else
+ } > IRAM
+#endif
.ibss (NOLOAD) :
{
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S
index a0b5a5abfb..ba5daa9117 100755
--- a/firmware/target/arm/tms320dm320/crt0.S
+++ b/firmware/target/arm/tms320dm320/crt0.S
@@ -44,6 +44,7 @@ start:
msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
+#ifndef CREATIVE_ZVx
/* Copy exception handler code to address 0 */
ldr r2, =_vectorsstart
ldr r3, =_vectorsend
@@ -53,6 +54,7 @@ start:
ldrhi r5, [r4], #4
strhi r5, [r2], #4
bhi 1b
+#endif
/* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */
mrc p15, 0, r0, c1, c0, 0
@@ -105,6 +107,7 @@ start:
strhi r4, [r2], #4
bhi 1b
+#ifndef CREATIVE_ZVx
/* Copy the IRAM */
ldr r2, =_iramcopy
ldr r3, =_iramstart
@@ -114,6 +117,7 @@ start:
ldrhi r5, [r2], #4
strhi r5, [r3], #4
bhi 1b
+#endif
#endif /* !BOOTLOADER,!STUB */
/* Initialise bss section to zero */