diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2008-04-06 04:34:57 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2008-04-06 04:34:57 +0000 |
| commit | 05099149f193cac0c81b0129c17feb78b1a9681a (patch) | |
| tree | 3dd5494dd494bcb4490ddcedef99e9f3a895cd3f /firmware/target/arm/tcc780x | |
| parent | be698f086de4641a45dffd9289671588c2391a3c (diff) | |
Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tcc780x')
| -rw-r--r-- | firmware/target/arm/tcc780x/ata-nand-tcc780x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/tcc780x/ata-nand-tcc780x.c b/firmware/target/arm/tcc780x/ata-nand-tcc780x.c index f6d1df96ce..b47444f3a8 100644 --- a/firmware/target/arm/tcc780x/ata-nand-tcc780x.c +++ b/firmware/target/arm/tcc780x/ata-nand-tcc780x.c @@ -42,7 +42,7 @@ static bool initialized = false; static long next_yield = 0; #define MIN_YIELD_PERIOD 2000 -static struct mutex ata_mtx NOCACHEBSS_ATTR; +static struct mutex ata_mtx SHAREDBSS_ATTR; #define SECTOR_SIZE 512 |