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| author | Andree Buschmann <AndreeBuschmann@t-online.de> | 2010-11-21 12:27:01 +0000 |
|---|---|---|
| committer | Andree Buschmann <AndreeBuschmann@t-online.de> | 2010-11-21 12:27:01 +0000 |
| commit | eef21cb18ae4bc7cdf83830554a848e0c733a73d (patch) | |
| tree | db04e994c7be9d634a49245928a99f6888e576b5 /firmware/target/arm/system-target.h | |
| parent | f54cbfa1647a1bcacb7998e0e19b17f0d1bde84a (diff) | |
Change alignment macros to allow further performance optimization. Define the CACHEALIGN macros for all ARM CPUs, the used alignment size is derived from CACHEALIGN_BITS which has been defined for each supported ARM CPU with r28619. The default alignment size for ARM is set to 32 bytes as new -- not yet supported -- ARM CPUs will most probably need this alignment. To be able to differ between ARM and other CPUs a new macro called MEM_ALIGN_ATTR is introduced. This equals CACHEALIGN_ATTR for ARM, 16 byte alignment for Coldfire and is kept empty for other CPUs. MEM_ALIGN_ATTR is available system wide. From measurements it is expected that the usage of MEM_ALIGN_ATTR can give significant performance gain on ARM11 CPUs.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28625 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-target.h')
| -rw-r--r-- | firmware/target/arm/system-target.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 1e573be291..3e3eab8f8d 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h @@ -158,10 +158,6 @@ static inline void wake_core(int core) ((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR)) #endif /* BOOTLOADER */ -/* Certain data needs to be out of the way of cache line interference - * such as data for COP use or for use with UNCACHED_ADDR */ -#define PROC_NEEDS_CACHEALIGN - #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) #define STORAGE_WANTS_ALIGN #endif |