diff options
| author | Bob Cousins <bobc@rockbox.org> | 2009-11-03 13:50:52 +0000 |
|---|---|---|
| committer | Bob Cousins <bobc@rockbox.org> | 2009-11-03 13:50:52 +0000 |
| commit | deb1b0e51c59518a6152b9a4b1f24004545c5c57 (patch) | |
| tree | 3feb40c5156b777fd5383669ab95f0caf6165bdf /firmware/target/arm/s3c2440 | |
| parent | bb9808b8afe1e95b0d7734840e64a91a0da3fe9b (diff) | |
Improvements to mini2440 audio; change CPU freq to 406MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23495 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s3c2440')
| -rw-r--r-- | firmware/target/arm/s3c2440/crt0.S | 6 | ||||
| -rw-r--r-- | firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | 1 | ||||
| -rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 22 |
3 files changed, 16 insertions, 13 deletions
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S index 3110c88be0..2188bc07da 100644 --- a/firmware/target/arm/s3c2440/crt0.S +++ b/firmware/target/arm/s3c2440/crt0.S @@ -138,13 +138,11 @@ /* For Mini2440 board or compatible */ /* Clock and Power Management setup values */ +/* NB: clock settings must match values in s3c2440/system-target.h */ #define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */ #define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */ -#define VAL_MPLLCON 0x0007F021 /* FCLK = 405 MHz */ +#define VAL_MPLLCON 0x000C3041 /* FCLK = 406 MHz */ -#define FCLK 405000000 -#define HCLK (FCLK/4) /* = 101,250,000 */ -#define PCLK (HCLK/2) /* = 50,625,000 */ /* Memory Controller setup */ #define VAL_BWSCON 0x22111112 diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c index 9c898f88d9..7779639c8f 100644 --- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c +++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c @@ -48,7 +48,6 @@ static struct /* [prescaler, master clock rate] */ static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = { - [HW_FREQ_64] = { 2, IISMOD_MASTER_CLOCK_256FS }, [HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS }, [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS }, [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS }, diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index cf3db301eb..7bb49c01c4 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h @@ -24,13 +24,18 @@ #include "system-arm.h"
#include "mmu-arm.h"
-/* TODO: Needs checking/porting */
+/* NB: These values must match the register settings in s3c2440/crt0.S */ #ifdef GIGABEAT_F
#define CPUFREQ_DEFAULT 98784000
#define CPUFREQ_NORMAL 98784000
#define CPUFREQ_MAX 296352000
+ /* Uses 1:3:6 */ + #define FCLK CPUFREQ_MAX + #define HCLK (FCLK/3) /* = 98,784,000 */ + #define PCLK (HCLK/2) /* = 49,392,000 */ + #ifdef BOOTLOADER
/* All addresses within rockbox are in IRAM in the bootloader so
are therefore uncached */
@@ -42,17 +47,18 @@ #elif defined(MINI2440)
- #define CPUFREQ_DEFAULT 101250000
- #define CPUFREQ_NORMAL 101250000
- #define CPUFREQ_MAX 405000000
+ /* Uses 1:4:8 */ + #define FCLK 406000000 + #define HCLK (FCLK/4) /* = 101,250,000 */ + #define PCLK (HCLK/2) /* = 50,625,000 */ +
+ #define CPUFREQ_DEFAULT FCLK /* 406 MHz */ + #define CPUFREQ_NORMAL (FCLK/4)/* 101.25 MHz */ + #define CPUFREQ_MAX FCLK /* 406 MHz */ #define UNCACHED_BASE_ADDR 0x30000000
#define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
- #define FCLK 405000000
- #define HCLK (FCLK/4) /* = 101,250,000 */
- #define PCLK (HCLK/2) /* = 50,625,000 */
-
#else
#error Unknown target
#endif
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