diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2010-05-04 10:07:53 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2010-05-04 10:07:53 +0000 |
| commit | 931e06de64100e28031627964321da3fdb449378 (patch) | |
| tree | 72a073d7ec3ede9554b394887d43d19fda6e8177 /firmware/target/arm/imx31/gigabeat-s | |
| parent | 7480afb3c59f4aebff262e1ce47395a3924ca994 (diff) | |
i.MX31/Gigabeat S: Actually enable DPTC which can set optimal voltage for 528MHz. Requires an SPI and PMIC interface rework because of the low-latency needs for the DPTC to work best with minimal panicing. SPI can work with multitasking and asynchronously from interrupt handlers or normal code.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25800 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s')
3 files changed, 2 insertions, 5 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c index 52293228f8..f7bc0ed37c 100644 --- a/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c @@ -71,7 +71,7 @@ unsigned short adc_read(int channel) /* Read all 8 channels that are converted - two channels in each * word. */ - mc13783_read_regset(reg_array, channels[input_select], 4); + mc13783_read_regs(reg_array, channels[input_select], 4); last_adc_read[input_select] = current_tick; } diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c index ab14a3c025..95f894bbce 100644 --- a/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c @@ -143,7 +143,7 @@ void _backlight_on(void) data[1] |= backlight_pwm_bits; /* Write regs within 30us of each other (requires single xfer) */ - mc13783_write_regset(regs, data, 2); + mc13783_write_regs(regs, data, 2); } } diff --git a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h index 2356e23252..4876736a2b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h @@ -75,9 +75,6 @@ /* Define mask of which reference circuits are employed for DPTC */ #define DPTC_DRCE_MASK (CCM_PMCR0_DRCE1 | CCM_PMCR0_DRCE3) -/* When panicing, this working point is used */ -#define DPTC_PANIC_WP - /* Due to a hardware bug in chip revisions < 2.0, when switching between * Serial and MCU PLLs, DVFS forces the target PLL to go into reset and * relock, only post divider frequency scaling is possible. |