diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2009-03-09 04:25:25 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2009-03-09 04:25:25 +0000 |
| commit | d1adf35e626cd9717cab2de17b029d3c8790ce6e (patch) | |
| tree | 26c8e3781bb5d906b4a737dea0439dae460047ab /firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c | |
| parent | de910d862c166c9c73ccc01b6a6dc0884c7037ae (diff) | |
Gigabeat S: Switch SSI1 and 2 around so that playback can use the shared peripheral DMA with SSI2 which doesn't require use of the peripheral DMA unit-- SSI2 is mapped to the SDMA core address space. Fix some break keywords in get_script_pc(). Use the patched script for mcu_2_app (BSP appears to have neglected to update that). Use _SHP instead of _SP for shared peripheral constants (consistency).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20254 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c')
| -rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c index e307057978..542f6eb633 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c @@ -44,17 +44,17 @@ void audiohw_init(void) /* How SYSCLK for codec is derived (USBPLL=338.688MHz). * * SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0): - * 338688000Hz / 5 = 67737600Hz = ssi2_clk + * 338688000Hz / 5 = 67737600Hz = ssi1_clk * * SSI bit clock dividers (DIV2=1, PSR=0, PM=0): - * ssi2_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK) + * ssi1_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK) * * WM Codec post divider (MCLKDIV=1.5): * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK */ imx31_regmod32(&CLKCTL_PDR1, - PDR1_SSI1_PODFw(64-1) | PDR1_SSI2_PODFw(5-1) | - PDR1_SSI1_PRE_PODFw(8-1) | PDR1_SSI2_PRE_PODFw(1-1), + PDR1_SSI1_PODFw(5-1) | PDR1_SSI2_PODFw(64-1) | + PDR1_SSI1_PRE_PODFw(1-1) | PDR1_SSI2_PRE_PODFw(8-1), PDR1_SSI1_PODF | PDR1_SSI2_PODF | PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF); |