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authorBertrik Sikken <bertrik@sikken.nl>2011-09-18 15:33:19 +0000
committerBertrik Sikken <bertrik@sikken.nl>2011-09-18 15:33:19 +0000
commit1d1e8e4eb723f34e50aaf3ffcff348367817bc52 (patch)
treef656af6c729c13baccd20b6e0b616d5d4ec1b02c /firmware/target/arm/as3525
parent382c6974e022be679b3d635f95e92e49ee86aac8 (diff)
Sansa AMSv2: initialise PMU (power management unit), inspired by how the OF does it
Differences in PMU settings: - explicitly disable the PLL inside the PMU (we don't use it) - don't increase the PVDD1/AVDD17 voltages because the impact on runtime is still unclear git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30571 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r--firmware/target/arm/as3525/system-as3525.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 8f64597f4f..58f08a7d19 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -270,6 +270,23 @@ void system_init(void)
dma_init();
ascodec_init();
+
+#if (CONFIG_CPU == AS3525v2)
+ /* PLL: disable audio PLL, we use MCLK already */
+ ascodec_write_pmu(0x1A, 7, 0x02);
+ /* DCDC_Cntr: set switching speed of CVDD1/2 power supplies to 1 MHz */
+ ascodec_write_pmu(0x17, 7, 0x30);
+ /* Out_Cntr2: set drive strength of 24 MHz and 32 kHz clocks to 1 mA */
+ ascodec_write_pmu(0x1A, 2, 0xCC);
+ /* CHGVBUS2: set VBUS threshold to 3.18V and EOC threshold to 30% CC */
+ ascodec_write_pmu(0x19, 2, 0x41);
+#if 0 /* don't set higher voltage until impact on runtime has been checked */
+ /* PVDD1: set PVDD1 power supply to 2.5 V */
+ ascodec_write_pmu(0x18, 1, 0x35);
+ /* AVDD17: set AVDD17 power supply to 2.5V */
+ ascodec_write_pmu(0x18, 7, 0x31);
+#endif
+#endif /* (CONFIG_CPU == AS3525v2) */
#ifndef BOOTLOADER
/* setup isr for microsd monitoring and for fuzev2 scrollwheel irq */