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authorRafaël Carré <rafael.carre@gmail.com>2009-11-24 12:05:53 +0000
committerRafaël Carré <rafael.carre@gmail.com>2009-11-24 12:05:53 +0000
commited13fd6dca3503b4513ba7b6a61b01a4e59fd363 (patch)
tree6ef67348cb49fe7fde7aac42c0ba5c0da49874ce /firmware/target/arm/as3525/timer-as3525.c
parent4314ceb73b68cc36e28e8d3711159578b0404c8c (diff)
Sansa AMS: VIC_INT_ENABLE register is not a mask
When read it returns all enabled interrupt sources When written it enables interrupt sources for each bit set So just like VIC_INT_EN_CLEAR, we don't have to read the previous value before writing to it (VIC_INT_EN_CLEAR is write-only anyway) Thanks to Fred Bauer for spotting git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23734 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/timer-as3525.c')
-rw-r--r--firmware/target/arm/as3525/timer-as3525.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/timer-as3525.c b/firmware/target/arm/as3525/timer-as3525.c
index 673e3b8f47..f5ff60e0f8 100644
--- a/firmware/target/arm/as3525/timer-as3525.c
+++ b/firmware/target/arm/as3525/timer-as3525.c
@@ -56,7 +56,7 @@ bool timer_set(long cycles, bool start)
bool timer_start(void)
{
CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */
- VIC_INT_ENABLE |= INTERRUPT_TIMER1;
+ VIC_INT_ENABLE = INTERRUPT_TIMER1;
return true;
}