diff options
| author | Rafaël Carré <rafael.carre@gmail.com> | 2009-11-01 23:35:34 +0000 |
|---|---|---|
| committer | Rafaël Carré <rafael.carre@gmail.com> | 2009-11-01 23:35:34 +0000 |
| commit | f64a3fe149830e54e75a9847337b08c73e827b2a (patch) | |
| tree | 84cf903a64ab4749985bceb79d1044e522447ce6 /firmware/target/arm/as3525/clock-target.h | |
| parent | e28bfd1349ca813cf34d8b327e21e128a6badba1 (diff) | |
Sansa AMS PCM: remove runtime sanity checks
Unaligned memory ops will cause a data abort anyway
Make the check for samplerate at buildtime
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23480 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
| -rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 560e067510..81926c1884 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -132,21 +132,35 @@ #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ #error PCLK frequency is too low : clock divider will not fit ! #endif + /* AS3525_DBOP_FREQ */ #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ #error DBOP frequency is too low : clock divider will not fit ! #endif + /* AS3525_IDE_FREQ */ #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ #error IDE frequency is too low : clock divider will not fit ! #endif + /* AS3525_I2C_FREQ */ #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ #error I2C frequency is too low : clock divider will not fit ! #endif + /* AS3525_SD_IDENT_FREQ */ #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! #endif +/* I2SIN / I2SOUT frequencies */ +/* low samplerate */ +#if ((AS3525_PLLA_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */ +#error PLLA frequency is too low for 8kHz samplerate ! +#endif +/* high samplerate */ +#if ((AS3525_PLLA_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */ +#error PLLA frequency is too high for 96kHz samplerate ! +#endif + #endif /* CLOCK_TARGET_H */ |