diff options
| author | Cástor Muñoz <cmvidal@gmail.com> | 2016-08-12 02:37:45 +0200 |
|---|---|---|
| committer | Cástor Muñoz <cmvidal@gmail.com> | 2016-08-12 14:17:46 +0200 |
| commit | adbd2969e6e6fd584d46ef60a3fa40bf878d7e00 (patch) | |
| tree | 628a89d0e63cd338bbd741702c9b36010f679437 /firmware/export | |
| parent | a25d0c58aa801087e80b479a7f536d519a422891 (diff) | |
iPod Classic: ADC updates
Add code to read USB D+/D- and accessory ADCs, it is shown in HW
debug menu, might be useful in future for RB and/or the bootloader
to identify external USB chargers.
Change-Id: Ia48ca5e06bb7ddc52bb55abedde6734653ce8dba
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/pcf5063x.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/firmware/export/pcf5063x.h b/firmware/export/pcf5063x.h index f5f177ace7..2751b67b57 100644 --- a/firmware/export/pcf5063x.h +++ b/firmware/export/pcf5063x.h @@ -198,12 +198,12 @@ enum pcf5063X_reg_mbcc2 { enum pcf5063X_reg_adcc1 { PCF5063X_ADCC1_ADCSTART = 0x01, - PCF5063X_ADCC1_RES_10BIT = 0x02, + PCF5063X_ADCC1_RES_10BIT = 0x00, + PCF5063X_ADCC1_RES_8BIT = 0x02, PCF5063X_ADCC1_AVERAGE_NO = 0x00, PCF5063X_ADCC1_AVERAGE_4 = 0x04, PCF5063X_ADCC1_AVERAGE_8 = 0x08, PCF5063X_ADCC1_AVERAGE_16 = 0x0c, - PCF5063X_ADCC1_MUX_BATSNS_RES = 0x00, PCF5063X_ADCC1_MUX_BATSNS_SUBTR = 0x10, PCF5063X_ADCC1_MUX_ADCIN2_RES = 0x20, @@ -211,6 +211,7 @@ enum pcf5063X_reg_adcc1 { PCF5063X_ADCC1_MUX_BATTEMP = 0x60, PCF5063X_ADCC1_MUX_ADCIN1 = 0x70, }; +#define PCF5063X_ADCC1_RES_MASK 0x02 #define PCF5063X_ADCC1_AVERAGE_MASK 0x0c #define PCF5063X_ADCC1_ADCMUX_MASK 0xf0 @@ -219,9 +220,11 @@ enum pcf5063X_reg_adcc2 { PCF5063X_ADCC2_RATIO_BATTEMP = 0x01, PCF5063X_ADCC2_RATIO_ADCIN1 = 0x02, PCF5063X_ADCC2_RATIO_BOTH = 0x03, + PCF5063X_ADCC2_RATIOSETTL_10US = 0x00, PCF5063X_ADCC2_RATIOSETTL_100US = 0x04, }; #define PCF5063X_ADCC2_RATIO_MASK 0x03 +#define PCF5063X_ADCC2_RATIOSETTL_MASK 0x04 enum pcf5063X_reg_adcc3 { PCF5063X_ADCC3_ACCSW_EN = 0x01, @@ -229,6 +232,7 @@ enum pcf5063X_reg_adcc3 { PCF5063X_ADCC3_RES_DIV_TWO = 0x10, PCF5063X_ADCC3_RES_DIV_THREE = 0x00, }; +#define PCF5063X_ADCC3_RES_DIV_MASK 0x10 enum pcf5063X_reg_adcs3 { PCF5063X_ADCS3_REF_NTCSW = 0x00, |