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authorMichael Sevakis <jethead71@rockbox.org>2011-12-17 07:27:24 +0000
committerMichael Sevakis <jethead71@rockbox.org>2011-12-17 07:27:24 +0000
commit6a67707b5ec3b2c649c401550bb7fdef2b7c8d07 (patch)
treebfe31942a4abbaac09ad0f4226effdcef8bf097e /firmware/export
parent43d7a75369286dc3b39b858df34f66b0b45de34e (diff)
Commit to certain names for cache coherency APIs and discard the aliases.
Wouldn't surprise me a bit to get some non-green. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r--firmware/export/load_code.h2
-rw-r--r--firmware/export/system.h29
2 files changed, 1 insertions, 30 deletions
diff --git a/firmware/export/load_code.h b/firmware/export/load_code.h
index 55ce601ee5..6f8505aba7 100644
--- a/firmware/export/load_code.h
+++ b/firmware/export/load_code.h
@@ -35,7 +35,7 @@ static inline void *lc_open_from_mem(void* addr, size_t blob_size)
{
(void)blob_size;
/* commit dcache and discard icache */
- cpucache_invalidate();
+ commit_discard_idcache();
return addr;
}
static inline void *lc_get_header(void *handle) { return handle; }
diff --git a/firmware/export/system.h b/firmware/export/system.h
index aa079940d1..1055c65b60 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -302,35 +302,6 @@ static inline uint32_t swaw32_hw(uint32_t value)
#define DISABLE_INTERRUPTS HIGHEST_IRQ_LEVEL
#endif
-/* Just define these as empty if not declared */
-#ifdef HAVE_CPUCACHE_INVALIDATE
-void cpucache_commit_discard(void);
-/* deprecated alias */
-void cpucache_invalidate(void);
-#else
-static inline void cpucache_commit_discard(void)
-{
-}
-/* deprecated alias */
-static inline void cpucache_invalidate(void)
-{
-}
-#endif
-
-#ifdef HAVE_CPUCACHE_FLUSH
-void cpucache_commit(void);
-/* deprecated alias */
-void cpucache_flush(void);
-#else
-static inline void cpucache_commit(void)
-{
-}
-/* deprecated alias */
-static inline void cpucache_flush(void)
-{
-}
-#endif
-
/* Define this, if the CPU may take advantage of cache aligment. Is enabled
* for all ARM CPUs. */
#ifdef CPU_ARM