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authorMichael Sevakis <jethead71@rockbox.org>2008-12-12 11:01:07 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-12-12 11:01:07 +0000
commite69d567d9ebf7d236ff9663b11ac396cc71dcd75 (patch)
tree093b9d1bc979d79be1fcd0daac1d8daf8ac55503 /firmware/export/uda1380.h
parent0ad97d13fc52b28de566dc0ddaf7245583eec2cc (diff)
Bring consistency to pcm implementation and samplerate handling. Less low-level duplication. A small test_sampr fix so it works on coldfire again.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19400 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/uda1380.h')
-rw-r--r--firmware/export/uda1380.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/firmware/export/uda1380.h b/firmware/export/uda1380.h
index 26b13a968f..af2b579a60 100644
--- a/firmware/export/uda1380.h
+++ b/firmware/export/uda1380.h
@@ -36,6 +36,8 @@ extern void audiohw_set_mixer_vol(int channel1, int channel2);
/**
* Sets frequency settings for DAC and ADC relative to MCLK
+ * For Coldfire IIS dividers, 11.2896MHz, codec as slave with
+ * PLL enabled.
*
* Selection for frequency ranges:
* Fs: range: with:
@@ -44,7 +46,7 @@ extern void audiohw_set_mixer_vol(int channel1, int channel2);
* 44100: 2 = 25 to 50 SCLK, LRCK: Audio Clk / 4 (default)
* 88200: 3 = 50 to 100 SCLK, LRCK: Audio Clk / 2
*/
-extern void audiohw_set_frequency(unsigned fsel);
+extern void audiohw_set_frequency(int fsel);
#define UDA1380_ADDR 0x30