diff options
| author | Andree Buschmann <AndreeBuschmann@t-online.de> | 2010-12-11 22:56:12 +0000 |
|---|---|---|
| committer | Andree Buschmann <AndreeBuschmann@t-online.de> | 2010-12-11 22:56:12 +0000 |
| commit | 08bcbd08d2b8229c6ea54c02d0805376bc75757d (patch) | |
| tree | a15a94e278fc6f1139743d0b3b5f178076740fc7 /firmware/export/s5l8700.h | |
| parent | 3eee12ed234da74243c3e90fbd5f4f35256370c7 (diff) | |
S5L870x LCD interface registers are 32 bit.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28798 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/s5l8700.h')
| -rw-r--r-- | firmware/export/s5l8700.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 47b34808b6..e8f4bc70c7 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h @@ -609,17 +609,17 @@ #define LCD_BASE 0x38600000 #endif -#define LCD_CON (*(REG16_PTR_T)(LCD_BASE+0x00)) /* Control register. */ -#define LCD_WCMD (*(REG16_PTR_T)(LCD_BASE+0x04)) /* Write command register. */ -#define LCD_RCMD (*(REG16_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */ -#define LCD_RDATA (*(REG16_PTR_T)(LCD_BASE+0x10)) /* Read data register. */ -#define LCD_DBUFF (*(REG16_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */ -#define LCD_INTCON (*(REG16_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */ -#define LCD_STATUS (*(REG16_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */ -#define LCD_PHTIME (*(REG16_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */ -#define LCD_RST_TIME (*(REG16_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */ -#define LCD_DRV_RST (*(REG16_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */ -#define LCD_WDATA (*(REG16_PTR_T)(LCD_BASE+0x40)) /* Write data register FIXME */ +#define LCD_CON (*(REG32_PTR_T)(LCD_BASE+0x00)) /* Control register. */ +#define LCD_WCMD (*(REG32_PTR_T)(LCD_BASE+0x04)) /* Write command register. */ +#define LCD_RCMD (*(REG32_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */ +#define LCD_RDATA (*(REG32_PTR_T)(LCD_BASE+0x10)) /* Read data register. */ +#define LCD_DBUFF (*(REG32_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */ +#define LCD_INTCON (*(REG32_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */ +#define LCD_STATUS (*(REG32_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */ +#define LCD_PHTIME (*(REG32_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */ +#define LCD_RST_TIME (*(REG32_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */ +#define LCD_DRV_RST (*(REG32_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */ +#define LCD_WDATA (*(REG32_PTR_T)(LCD_BASE+0x40)) /* Write data register (0x40...0x5C) FIXME */ /* 27. CLCD CONTROLLER */ #define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ |