diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2006-11-23 19:21:15 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2006-11-23 19:21:15 +0000 |
| commit | ab1861a3c2c06cf3edff7c42348d117f21235e48 (patch) | |
| tree | e41eddf45f5348a2d954ac97984fbf7a7c61bd6c /firmware/drivers | |
| parent | 069c54d5d87378ccd73d84be2606ec2ab654bc21 (diff) | |
iRiver/iAudio: Added audio_set_recording gain and sound_default to plugin API. Simplified plugin recording by target/-ing some audio functions. UDA1380 records with WSPLL as a result.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11577 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers')
| -rw-r--r-- | firmware/drivers/uda1380.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c index d6dfe6623b..82bf6d1ae1 100644 --- a/firmware/drivers/uda1380.c +++ b/firmware/drivers/uda1380.c @@ -272,7 +272,7 @@ void uda1380_enable_recording(bool source_mic) { /* VGA_GAIN: 0=0 dB, F=30dB */ /* Output of left ADC is fed into right bitstream */ - uda1380_regs[REG_PWR] &= ~(PON_PLL | PON_PGAR | PON_ADCR); + uda1380_regs[REG_PWR] &= ~(PON_PGAR | PON_ADCR); uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL); uda1380_regs[REG_ADC] &= ~SKIP_DCFIL; uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK) @@ -282,7 +282,7 @@ void uda1380_enable_recording(bool source_mic) else { /* PGA_GAIN: 0=0 dB, F=24dB */ - uda1380_regs[REG_PWR] &= ~(PON_PLL | PON_LNA); + uda1380_regs[REG_PWR] &= ~PON_LNA; uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL | PON_PGAR | PON_ADCR); uda1380_write_reg(REG_ADC, EN_DCFIL); @@ -305,8 +305,9 @@ void uda1380_disable_recording(void) uda1380_write_reg(REG_I2S, I2S_IFMT_IIS); - uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR | PON_PGAL | PON_PGAR); - uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PLL); + uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR | + PON_PGAL | PON_PGAR); + uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]); uda1380_regs[REG_0] &= ~EN_ADC; uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); |