diff options
| author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-09 07:46:42 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-09 07:46:42 +0000 |
| commit | 62c768c0db601fa1cc8532bb583060f2a8080453 (patch) | |
| tree | 96c83ffdb5f8b0edc3dc1e0f6fc417a60d607bc9 /firmware/crt0.S | |
| parent | f69c77933c7fca7b72dfc6aa94cbe03651a149f8 (diff) | |
Recovered from my major brain failure and reverted to using the same load address for both H110 and H120/140
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7082 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/crt0.S')
| -rw-r--r-- | firmware/crt0.S | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 749039bc37..65577e02b9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S @@ -190,7 +190,7 @@ irq_handler: /* Set up the DRAM controller. The refresh is based on the 11.2896MHz clock (5.6448MHz bus frequency). We haven't yet started the PLL */ -#ifdef IRIVER_H100 +#if MEM < 32 move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ #else move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ @@ -205,8 +205,8 @@ irq_handler: In our case this means that we set the base address 16M ahead and use a 64M mask. */ -#ifdef IRIVER_H100 - move.l #0x30002320,%d0 /* DACR0 - Base 0x30000000, Banks on 21 and up, +#if MEM < 32 + move.l #0x31002320,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, CAS latency 1, No refresh yet */ move.l %d0,(0x108,%a0) move.l #0x00fc0001,%d0 /* Size: 16M */ @@ -224,10 +224,7 @@ irq_handler: or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a Precharge command */ move.l #0xabcd1234,%d0 - move.l %d0,0x30000000 /* Issue precharge command by writing somewhere - in the SDRAM. (The 0x30000000 address is - mirrored on 32Mbyte devices so it works on - all models.) */ + move.l %d0,0x31000000 /* Issue precharge command */ /* Let it refresh */ move.l #1000,%d0 @@ -245,7 +242,7 @@ irq_handler: or.l %d0,(0x108,%a0) move.l #0xabcd1234,%d0 - move.l %d0,0x30000800 /* A12=1 means CASL=1 (a0 is not connected) */ + move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ move.l #0xffffffbf,%d0 and.l %d0,(0x108,%a0) /* Back to normal, the DRAM is now ready */ @@ -260,11 +257,7 @@ irq_handler: movec.l %d0,%cacr /* Cache enabled in SDRAM only, buffered writes enabled */ -#ifdef IRIVER_H100 - move.l #0x3003c020,%d0 -#else move.l #0x3103c020,%d0 -#endif movec.l %d0,%acr0 moveq.l #0,%d0 movec.l %d0,%acr1 |