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| author | Marcin Bukat <marcin.bukat@gmail.com> | 2014-07-23 22:08:24 +0200 |
|---|---|---|
| committer | Marcin Bukat <marcin.bukat@gmail.com> | 2014-07-23 22:11:10 +0200 |
| commit | 345841aa5657aa2899dd9a72547fcb0cfeaf8e80 (patch) | |
| tree | f6403e45ca6a04f9f03c0c4c98b7c95b489dcb3b | |
| parent | dcd8172f4f3de41f163a0a0fdc79565074a32c44 (diff) | |
rk27load: stage1 dram config fix #2
Change-Id: I5c4cf3dedab26e4cae05496bcae3a2d235d12e2f
| -rw-r--r-- | utils/rk27utils/rk27load/stage1/main.S | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/utils/rk27utils/rk27load/stage1/main.S b/utils/rk27utils/rk27load/stage1/main.S index 2564ad3cc4..e2cf2e5361 100644 --- a/utils/rk27utils/rk27load/stage1/main.S +++ b/utils/rk27utils/rk27load/stage1/main.S @@ -70,18 +70,16 @@ row_loop: str r7, [r0, #0x108] /* MCSDR_ADDCFG */ add r7, r5, #11 /* row_num_bits */ - mov r7, r3, lsl r7 /* 1<<row_num_bits */ - mla lr, r7, r6, r6 /* (1<<row_num_bits)*(1<<col_num_bits) + - * (1<<col_num_bits) (row1, col1 mem cell) - */ + mov lr, r3, lsl r7 /* 1<<row_num_bits */ + mul lr, lr, r6 /* (1<<row_num_bits)*(1<<col_num_bits) */ mov r7, #0 str r7, [r2] /* *(0x60000000) = 0 */ - str r2, [r2, lr] /* store test pattern */ + str r1, [r2, lr] /* store test pattern */ ldr r7, [r2] cmp r7, #0 /* check if beginning of dram is not touched */ - ldreq lr, [r2, lr] /* readback row1,col1 addr */ - cmpeq lr, r1 /* check if test pattern is valid */ + ldreq r7, [r2, lr] /* readback row1 addr */ + cmpeq r7, r1 /* check if test pattern is valid */ beq end subs r5, #1 bpl row_loop |