x1000: Remove some #ifdef SPL in the sfc/nand code

Change-Id: I554d590bfa700e521a74b5216e09f9673902d676

4 files changed, 12 insertions, 29 deletions

diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
index 26a8b840c9..1238d7e452 100644
--- a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
+++ b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
@@ -25,11 +25,6 @@
 /* The max page size (main + spare) of all NAND chips used by this target */
 #define NAND_MAX_PAGE_SIZE (2048 + 64)
 
-/* The clock source to use for the SFC controller. Note the SPL has special
- * handling which ignores this choice, so it only applies to bootloader & app.
- */
-#define NAND_CLOCK_SOURCE X1000_CLK_SCLK_A
-
 /* The clock speed to use for the SFC controller during chip identification */
 #define NAND_INIT_CLOCK_SPEED 150000000
 
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index e6d5b6e4c7..fc8d471559 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -73,7 +73,7 @@ int nand_open(void)
     /* Init hardware */
     sfc_open();
     sfc_set_dev_conf(NAND_INIT_SFC_DEV_CONF);
-    sfc_set_clock(NAND_CLOCK_SOURCE, NAND_INIT_CLOCK_SPEED);
+    sfc_set_clock(NAND_INIT_CLOCK_SPEED);
 
     /* Identify NAND chip */
     int status = 0;
@@ -103,7 +103,7 @@ int nand_open(void)
 
     /* Configure hardware and run init op */
     sfc_set_dev_conf(desc->data->dev_conf);
-    sfc_set_clock(NAND_CLOCK_SOURCE, desc->data->clock_freq);
+    sfc_set_clock(desc->data->clock_freq);
 
     if((status = desc->ops->open(&nand_driver)) < 0)
         goto _err;
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.c b/firmware/target/mips/ingenic_x1000/sfc-x1000.c
index 4a79be849e..3f1cb25f07 100644
--- a/firmware/target/mips/ingenic_x1000/sfc-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.c
@@ -33,18 +33,6 @@
  * simple, DMA is unconditionally disabled. */
 //#define NEED_SFC_DMA
 
-#if defined(BOOTLOADER_SPL)
-# if X1000_EXCLK_FREQ == 24000000
-#  define FIXED_CLK_FREQ  600000000
-#  define FIXED_CLK_SRC   X1000_CLK_MPLL
-# elif X1000_EXCLK_FREQ == 26000000
-#  define FIXED_CLK_FREQ  598000000
-#  define FIXED_CLK_SRC   X1000_CLK_MPLL
-# else
-#  error "bad EXCLK freq"
-# endif
-#endif
-
 #define FIFO_THRESH 31
 
 #define SFC_STATUS_PENDING (-1)
@@ -111,16 +99,16 @@ void sfc_close(void)
     jz_writef(CPM_CLKGR, SFC(1));
 }
 
-void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq)
+void sfc_set_clock(uint32_t freq)
 {
-    uint32_t in_freq;
-#ifdef FIXED_CLK_FREQ
-    /* Small optimization to save code space in SPL by not polling clock */
-    clksrc = FIXED_CLK_SRC;
-    in_freq = FIXED_CLK_FREQ;
-#else
-    in_freq = clk_get(clksrc);
-#endif
+    /* TODO: This is a hack so we can use MPLL in the SPL.
+     * There must be a better way to do this... */
+    x1000_clk_t clksrc = X1000_CLK_MPLL;
+    uint32_t in_freq = clk_get(clksrc);
+    if(in_freq < freq) {
+        clksrc = X1000_CLK_SCLK_A;
+        in_freq = clk_get(clksrc);
+    }
 
     uint32_t div = clk_calc_div(in_freq, freq);
     jz_writef(CPM_SSICDR, CE(1), CLKDIV(div - 1),
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.h b/firmware/target/mips/ingenic_x1000/sfc-x1000.h
index 283f171697..5784198b93 100644
--- a/firmware/target/mips/ingenic_x1000/sfc-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.h
@@ -99,7 +99,7 @@ extern void sfc_close(void);
 #define sfc_set_wp_enable(en) \
     jz_writef(SFC_GLB, WP_EN((en) ? 1 : 0))
 
-extern void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq);
+extern void sfc_set_clock(uint32_t freq);
 
 /* Execute an operation. Returns zero on success, nonzero on failure. */
 extern int sfc_exec(const sfc_op* op);