diff options
| author | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-02 00:34:44 +0000 |
|---|---|---|
| committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-02 00:34:44 +0000 |
| commit | 091f2a0c4f25a3fc45bf63939266d5562c85e7cf (patch) | |
| tree | 2b819f459fe3356983b56f2a26f5715301389158 | |
| parent | 311ae23a540a0918a769bca6e3c53ad0d4556273 (diff) | |
AS3525: disable interrupts, higher clock frequencies
fclk (CPU) at 240MHz
pclk (peripherals) at 64MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18972 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 45f36bda8c..a28ffc473e 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c @@ -201,7 +201,22 @@ void system_init(void) CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; #endif + CGU_PROC = 0; /* fclk 24 MHz */ + CGU_PERI &= ~0x7f; /* pclk 24 MHz */ + asm volatile( + "mrc p15, 0, r0, c1, c0 \n" + "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */ + "mcr p15, 0, r0, c1, c0 \n" + : : : "r0" ); + + CGU_PLLA = 0x4330; /* PLLA 384 MHz */ + CGU_PROC = (3<<2)|0x01; /* fclk = PLLA*5/8 = 240 MHz */ + + asm volatile( + "mrs r0, cpsr \n" + "orr r0, r0, #0x80 \n" /* disable interrupts */ + "msr cpsr, r0 \n" "mov r0, #0 \n" "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */ "mrc p15, 0, r0, c1, c0 \n" /* control register */ @@ -210,8 +225,9 @@ void system_init(void) "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); - sdram_init(); + + CGU_PERI |= (5<<2)|0x01; /* pclk = PLLA / 6 = 64 MHz */ } void system_reboot(void) |