1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
|
[
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x01",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS",
"BriefDescription": "A snoop misses in some processor core.",
"PublicDescription": "A snoop misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x02",
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",
"BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
"PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x04",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT",
"BriefDescription": "A snoop hits a non-modified line in some processor core.",
"PublicDescription": "A snoop hits a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x08",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM",
"BriefDescription": "A snoop hits a modified line in some processor core.",
"PublicDescription": "A snoop hits a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x10",
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",
"BriefDescription": "A snoop invalidates a modified line in some processor core.",
"PublicDescription": "A snoop invalidates a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x20",
"EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x40",
"EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x80",
"EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x01",
"EventName": "UNC_CBO_CACHE_LOOKUP.M",
"BriefDescription": "LLC lookup request that access cache and found line in M-state.",
"PublicDescription": "LLC lookup request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x02",
"EventName": "UNC_CBO_CACHE_LOOKUP.E",
"BriefDescription": "LLC lookup request that access cache and found line in E-state.",
"PublicDescription": "LLC lookup request that access cache and found line in E-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x04",
"EventName": "UNC_CBO_CACHE_LOOKUP.S",
"BriefDescription": "LLC lookup request that access cache and found line in S-state.",
"PublicDescription": "LLC lookup request that access cache and found line in S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x08",
"EventName": "UNC_CBO_CACHE_LOOKUP.I",
"BriefDescription": "LLC lookup request that access cache and found line in I-state.",
"PublicDescription": "LLC lookup request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x10",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",
"BriefDescription": "Filter on processor core initiated cacheable read requests.",
"PublicDescription": "Filter on processor core initiated cacheable read requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x20",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",
"BriefDescription": "Filter on processor core initiated cacheable write requests.",
"PublicDescription": "Filter on processor core initiated cacheable write requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x40",
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",
"BriefDescription": "Filter on external snoop requests.",
"PublicDescription": "Filter on external snoop requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x80",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",
"BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
"PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x81",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x81",
"UMask": "0x20",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x81",
"UMask": "0x80",
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
"BriefDescription": "Counts the number of LLC evictions allocated.",
"PublicDescription": "Counts the number of LLC evictions allocated.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x83",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x84",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
"PublicDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "1",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0,1",
"CounterMask": "10",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "ARB",
"EventCode": "0x0",
"UMask": "0x01",
"EventName": "UNC_CLOCK.SOCKET",
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "Fixed",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x06",
"EventName": "UNC_CBO_CACHE_LOOKUP.ES",
"BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
"PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
}
]
|