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#ifndef _UAPI_ASM_POWERPC_PERF_REGS_H
#define _UAPI_ASM_POWERPC_PERF_REGS_H
enum perf_event_powerpc_regs {
PERF_REG_POWERPC_R0,
PERF_REG_POWERPC_R1,
PERF_REG_POWERPC_R2,
PERF_REG_POWERPC_R3,
PERF_REG_POWERPC_R4,
PERF_REG_POWERPC_R5,
PERF_REG_POWERPC_R6,
PERF_REG_POWERPC_R7,
PERF_REG_POWERPC_R8,
PERF_REG_POWERPC_R9,
PERF_REG_POWERPC_R10,
PERF_REG_POWERPC_R11,
PERF_REG_POWERPC_R12,
PERF_REG_POWERPC_R13,
PERF_REG_POWERPC_R14,
PERF_REG_POWERPC_R15,
PERF_REG_POWERPC_R16,
PERF_REG_POWERPC_R17,
PERF_REG_POWERPC_R18,
PERF_REG_POWERPC_R19,
PERF_REG_POWERPC_R20,
PERF_REG_POWERPC_R21,
PERF_REG_POWERPC_R22,
PERF_REG_POWERPC_R23,
PERF_REG_POWERPC_R24,
PERF_REG_POWERPC_R25,
PERF_REG_POWERPC_R26,
PERF_REG_POWERPC_R27,
PERF_REG_POWERPC_R28,
PERF_REG_POWERPC_R29,
PERF_REG_POWERPC_R30,
PERF_REG_POWERPC_R31,
PERF_REG_POWERPC_NIP,
PERF_REG_POWERPC_MSR,
PERF_REG_POWERPC_ORIG_R3,
PERF_REG_POWERPC_CTR,
PERF_REG_POWERPC_LINK,
PERF_REG_POWERPC_XER,
PERF_REG_POWERPC_CCR,
PERF_REG_POWERPC_SOFTE,
PERF_REG_POWERPC_TRAP,
PERF_REG_POWERPC_DAR,
PERF_REG_POWERPC_DSISR,
PERF_REG_POWERPC_MAX,
};
#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
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