1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
|
#include "headers.h"
#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
#define MIPS_CLOCK_REG 0x0f000820
//DDR INIT-133Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 //index for 0x0F007000
static struct bcm_ddr_setting asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F000800,0x00007212},
{0x0f000820,0x07F13FFF},
{0x0f000810,0x00000F95},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000840,0x0FFF1B00},
{0x0f000870,0x00000002},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
{0x0F00a04C,0x0000000C},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
{0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x02000007},
{0x0F007028,0x02020202},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
{0x0F007030,0x05000000},
{0x0F007034,0x00000003},
{0x0F007038,0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
{0x0F00703C,0x02101010},//ROB - 0x02101010,//0x02101018},
{0x0F007040,0x45751200},//ROB - 0x45751200,//0x450f1200},
{0x0F007044,0x110a0d00},//ROB - 0x110a0d00//0x111f0d00
{0x0F007048,0x081b0306},
{0x0F00704c,0x00000000},
{0x0F007050,0x0000001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x0010246c},
{0x0F007064,0x00000010},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00007000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
//# Enable BW improvement within memory controller
{0x0F007094,0x00000104},
//# Enable 2 ports within X-bar
{0x0F00A000,0x00000016},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
//80Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 //index for 0x0F007000
static struct bcm_ddr_setting asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000810,0x00000F95},
{0x0f000820,0x07f1ffff},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
{0x0F00a000,0x00000016},
{0x0F00a04C,0x0000000C},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01000000},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020000},
{0x0F007020,0x04020107},
{0x0F007024,0x00000007},
{0x0F007028,0x02020201},
{0x0F00702c,0x0204040a},
{0x0F007030,0x04000000},
{0x0F007034,0x00000002},
{0x0F007038,0x1F060200},
{0x0F00703C,0x1C22221F},
{0x0F007040,0x8A006600},
{0x0F007044,0x221a0800},
{0x0F007048,0x02690204},
{0x0F00704c,0x00000000},
{0x0F007050,0x0000001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x000A15D6},
{0x0F007064,0x0000000A},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00004000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
{0x0F007094,0x00000104},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
//100Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 //index for 0x0F007000
static struct bcm_ddr_setting asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F000800,0x00007008},
{0x0f000810,0x00000F95},
{0x0f000820,0x07F13E3F},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
//0x0f000840,0x0FFF1800,
{0x0f000840,0x0FFF1B00},
{0x0f000870,0x00000002},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
{0x0F00a04C,0x0000000C},
//# Enable 2 ports within X-bar
{0x0F00A000,0x00000016},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020001}, // POP - 0x00020000 Normal 0x01020000
{0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x00000007},
{0x0F007028,0x01020201},
{0x0F00702c,0x0204040A},
{0x0F007030,0x06000000},
{0x0F007034,0x00000004},
{0x0F007038,0x20080200},
{0x0F00703C,0x02030320},
{0x0F007040,0x6E7F1200},
{0x0F007044,0x01190A00},
{0x0F007048,0x06120305},//0x02690204 // 0x06120305
{0x0F00704c,0x00000000},
{0x0F007050,0x0000001C},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x00082ED6},
{0x0F007064,0x0000000A},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00005000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
//# Enable BW improvement within memory controller
{0x0F007094,0x00000104},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
//Net T3B DDR Settings
//DDR INIT-133Mhz
static struct bcm_ddr_setting asDPLL_266MHZ[] = {
{0x0F000800,0x00007212},
{0x0f000820,0x07F13FFF},
{0x0f000810,0x00000F95},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000840,0x0FFF1B00},
{0x0f000870,0x00000002}
};
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 //index for 0x0F007000
static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
{0x0f000810,0x00000F95},
{0x0f000810,0x00000F95},
{0x0f000810,0x00000F95},
{0x0f000820,0x07F13652},
{0x0f000840,0x0FFF0800},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000880,0x000003DD},
{0x0f000860,0x00000000},
// Changed source for X-bar and MIPS clock to APLL
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
//# Enable 2 ports within X-bar
{0x0F00A000,0x00000016},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
{0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x02000007},
{0x0F007028,0x02020202},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
{0x0F007030,0x05000000},
{0x0F007034,0x00000003},
{0x0F007038,0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
{0x0F00703C,0x02101012},//ROB - 0x02101010,//0x02101018},
{0x0F007040,0x457D1200},//ROB - 0x45751200,//0x450f1200},
{0x0F007044,0x11130d00},//ROB - 0x110a0d00//0x111f0d00
{0x0F007048,0x040D0306},
{0x0F00704c,0x00000000},
{0x0F007050,0x0000001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x0010246c},
{0x0F007064,0x00000012},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00007000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
//# Enable BW improvement within memory controller
{0x0F007094,0x00000104},
//# Enable start bit within memory controller
{0x0F007018,0x01010000},
};
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
{0x0f000810,0x00000F95},
{0x0f000820,0x07F13FFF},
{0x0f000840,0x0FFF1F00},
{0x0f000880,0x000003DD},
{0x0f000860,0x00000000},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
{0x0F00a000,0x00000016},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01000000},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020000},
{0x0F007020,0x04020107},
{0x0F007024,0x00000007},
{0x0F007028,0x02020201},
{0x0F00702c,0x0204040a},
{0x0F007030,0x04000000},
{0x0F007034,0x02000002},
{0x0F007038,0x1F060202},
{0x0F00703C,0x1C22221F},
{0x0F007040,0x8A006600},
{0x0F007044,0x221a0800},
{0x0F007048,0x02690204},
{0x0F00704c,0x00000000},
{0x0F007050,0x0100001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x000A15D6},
{0x0F007064,0x0000000A},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00004000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
{0x0F007094,0x00000104},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
//100Mhz
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 //index for 0x0F007000
static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
{0x0f000810,0x00000F95},
{0x0f000820,0x07F1369B},
{0x0f000840,0x0FFF0800},
{0x0f000880,0x000003DD},
{0x0f000860,0x00000000},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
//# Enable 2 ports within X-bar
{0x0F00A000,0x00000016},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020000}, // POP - 0x00020000 Normal 0x01020000
{0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x00000007},
{0x0F007028,0x01020201},
{0x0F00702c,0x0204040A},
{0x0F007030,0x06000000},
{0x0F007034,0x02000004},
{0x0F007038,0x20080200},
{0x0F00703C,0x02030320},
{0x0F007040,0x6E7F1200},
{0x0F007044,0x01190A00},
{0x0F007048,0x06120305},//0x02690204 // 0x06120305
{0x0F00704c,0x00000000},
{0x0F007050,0x0100001C},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x00082ED6},
{0x0F007064,0x0000000A},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00005000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
//# Enable BW improvement within memory controller
{0x0F007094,0x00000104},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 //index for 0x0F007000
static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0f000820,0x03F1365B},
{0x0f000810,0x00002F95},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000840,0x0FFF0000},
{0x0f000860,0x00000000},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
{0x0F00A000,0x00000016},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
{0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x02000007},
{0x0F007028,0x02020200},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
{0x0F007030,0x05000000},
{0x0F007034,0x00000003},
{0x0F007038,0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
{0x0F00703C,0x02101020},//ROB - 0x02101010,//0x02101018,
{0x0F007040,0x45711200},//ROB - 0x45751200,//0x450f1200,
{0x0F007044,0x110D0D00},//ROB - 0x110a0d00//0x111f0d00
{0x0F007048,0x04080306},
{0x0F00704c,0x00000000},
{0x0F007050,0x0100001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x0010245F},
{0x0F007064,0x00000010},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00007000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
{0x0F007088,0x01000001},
{0x0F00708c,0x00000101},
{0x0F007090,0x00000000},
//# Enable BW improvement within memory controller
{0x0F007094,0x00040000},
{0x0F007098,0x00000000},
{0x0F0070c8,0x00000104},
//# Enable 2 ports within X-bar
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 //index for 0x0F007000
static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810,0x00002F95},
{0x0f000820,0x03F1369B},
{0x0f000840,0x0fff0000},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000840,0x0FFF0000},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
{0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x00000007},
{0x0F007028,0x01020200},
{0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
{0x0F007030,0x06000000},
{0x0F007034,0x00000004},
{0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
{0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
{0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
{0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
{0x0F007048,0x03000305},
{0x0F00704c,0x00000000},
{0x0F007050,0x0100001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x00082ED6},
{0x0F007064,0x0000000A},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00005000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
{0x0F007088,0x01000001},
{0x0F00708c,0x00000101},
{0x0F007090,0x00000000},
{0x0F007094,0x00010000},
{0x0F007098,0x00000000},
{0x0F0070C8,0x00000104},
//# Enable 2 ports within X-bar
{0x0F00A000,0x00000016},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000820,0x07F13FFF},
{0x0f000810,0x00002F95},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
{0x0f000840,0x0FFF1F00},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0F00a084,0x1Cffffff},
{0x0F00a080,0x1C000000},
{0x0F00A000,0x00000016},
{0x0f007000,0x00010001},
{0x0f007004,0x01000000},
{0x0f007008,0x01000001},
{0x0f00700c,0x00000000},
{0x0f007010,0x01000000},
{0x0f007014,0x01000100},
{0x0f007018,0x01000000},
{0x0f00701c,0x01020000},
{0x0f007020,0x04020107},
{0x0f007024,0x00000007},
{0x0f007028,0x02020200},
{0x0f00702c,0x0204040a},
{0x0f007030,0x04000000},
{0x0f007034,0x00000002},
{0x0f007038,0x1d060200},
{0x0f00703c,0x1c22221d},
{0x0f007040,0x8A116600},
{0x0f007044,0x222d0800},
{0x0f007048,0x02690204},
{0x0f00704c,0x00000000},
{0x0f007050,0x0100001c},
{0x0f007054,0x00000000},
{0x0f007058,0x00000000},
{0x0f00705c,0x00000000},
{0x0f007060,0x000A15D6},
{0x0f007064,0x0000000A},
{0x0f007068,0x00000000},
{0x0f00706c,0x00000001},
{0x0f007070,0x00004000},
{0x0f007074,0x00000000},
{0x0f007078,0x00000000},
{0x0f00707c,0x00000000},
{0x0f007080,0x00000000},
{0x0f007084,0x00000000},
{0x0f007088,0x01000001},
{0x0f00708c,0x00000101},
{0x0f007090,0x00000000},
{0x0f007094,0x00010000},
{0x0f007098,0x00000000},
{0x0F0070C8,0x00000104},
{0x0F007018,0x01010000}
};
///T3 LP-B (UMA-B)
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 //index for 0x0F007000
static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
{0x0f000820,0x03F137DB},
{0x0f000810,0x01842795},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
{0x0f000840,0x0FFF0400},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0f003050,0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz
{0x0F00a084,0x1Cffffff},//Now dump from her in internal memory
{0x0F00a080,0x1C000000},
{0x0F00A000,0x00000016},
{0x0f007000,0x00010001},
{0x0f007004,0x01000001},
{0x0f007008,0x01000101},
{0x0f00700c,0x00000000},
{0x0f007010,0x01000100},
{0x0f007014,0x01000100},
{0x0f007018,0x01000000},
{0x0f00701c,0x01020000},
{0x0f007020,0x04030107},
{0x0f007024,0x02000007},
{0x0f007028,0x02020200},
{0x0f00702c,0x0206060a},
{0x0f007030,0x050d0d00},
{0x0f007034,0x00000003},
{0x0f007038,0x170a0200},
{0x0f00703c,0x02101012},
{0x0f007040,0x45161200},
{0x0f007044,0x11250c00},
{0x0f007048,0x04da0307},
{0x0f00704c,0x00000000},
{0x0f007050,0x0000001c},
{0x0f007054,0x00000000},
{0x0f007058,0x00000000},
{0x0f00705c,0x00000000},
{0x0f007060,0x00142bb6},
{0x0f007064,0x20430014},
{0x0f007068,0x00000000},
{0x0f00706c,0x00000001},
{0x0f007070,0x00009000},
{0x0f007074,0x00000000},
{0x0f007078,0x00000000},
{0x0f00707c,0x00000000},
{0x0f007080,0x00000000},
{0x0f007084,0x00000000},
{0x0f007088,0x01000001},
{0x0f00708c,0x00000101},
{0x0f007090,0x00000000},
{0x0f007094,0x00040000},
{0x0f007098,0x00000000},
{0x0F0070C8,0x00000104},
{0x0F007018,0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 //index for 0x0F007000
static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0f000820,0x03F1365B},
{0x0f000810,0x00002F95},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000840,0x0FFF0000},
{0x0f000860,0x00000000},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
{0x0F00a084,0x1Cffffff},//dump from here in internal memory
{0x0F00a080,0x1C000000},
{0x0F00A000,0x00000016},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
{0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x02000007},
{0x0F007028,0x02020200},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
{0x0F007030,0x05000000},
{0x0F007034,0x00000003},
{0x0F007038,0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
{0x0F00703C,0x02101017},//ROB - 0x02101010,//0x02101018,
{0x0F007040,0x45171200},//ROB - 0x45751200,//0x450f1200,
{0x0F007044,0x11290D00},//ROB - 0x110a0d00//0x111f0d00
{0x0F007048,0x04080306},
{0x0F00704c,0x00000000},
{0x0F007050,0x0100001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x0010245F},
{0x0F007064,0x00000010},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00007000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
{0x0F007088,0x01000001},
{0x0F00708c,0x00000101},
{0x0F007090,0x00000000},
//# Enable BW improvement within memory controller
{0x0F007094,0x00040000},
{0x0F007098,0x00000000},
{0x0F0070c8,0x00000104},
//# Enable 2 ports within X-bar
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 //index for 0x0F007000
static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810,0x00002F95},
{0x0f000820,0x03F1369B},
{0x0f000840,0x0fff0000},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
// Changed source for X-bar and MIPS clock to APLL
{0x0f000840,0x0FFF0000},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
{0x0F00a084,0x1Cffffff}, //dump from here in internal memory
{0x0F00a080,0x1C000000},
//Memcontroller Default values
{0x0F007000,0x00010001},
{0x0F007004,0x01010100},
{0x0F007008,0x01000001},
{0x0F00700c,0x00000000},
{0x0F007010,0x01000000},
{0x0F007014,0x01000100},
{0x0F007018,0x01000000},
{0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
{0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
{0x0F007024,0x00000007},
{0x0F007028,0x01020200},
{0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
{0x0F007030,0x06000000},
{0x0F007034,0x00000004},
{0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
{0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
{0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
{0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
{0x0F007048,0x03000305},
{0x0F00704c,0x00000000},
{0x0F007050,0x0100001c},
{0x0F007054,0x00000000},
{0x0F007058,0x00000000},
{0x0F00705c,0x00000000},
{0x0F007060,0x00082ED6},
{0x0F007064,0x0000000A},
{0x0F007068,0x00000000},
{0x0F00706c,0x00000001},
{0x0F007070,0x00005000},
{0x0F007074,0x00000000},
{0x0F007078,0x00000000},
{0x0F00707C,0x00000000},
{0x0F007080,0x00000000},
{0x0F007084,0x00000000},
{0x0F007088,0x01000001},
{0x0F00708c,0x00000101},
{0x0F007090,0x00000000},
{0x0F007094,0x00010000},
{0x0F007098,0x00000000},
{0x0F0070C8,0x00000104},
//# Enable 2 ports within X-bar
{0x0F00A000,0x00000016},
//# Enable start bit within memory controller
{0x0F007018,0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 //index for 0x0F007000
static struct bcm_ddr_setting asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000820,0x07F13FFF},
{0x0f000810,0x00002F95},
{0x0f000860,0x00000000},
{0x0f000880,0x000003DD},
{0x0f000840,0x0FFF1F00},
{0x0F00a044,0x1fffffff},
{0x0F00a040,0x1f000000},
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
{0x0F00a084,0x1Cffffff},// dump from here in internal memory
{0x0F00a080,0x1C000000},
{0x0F00A000,0x00000016},
{0x0f007000,0x00010001},
{0x0f007004,0x01000000},
{0x0f007008,0x01000001},
{0x0f00700c,0x00000000},
{0x0f007010,0x01000000},
{0x0f007014,0x01000100},
{0x0f007018,0x01000000},
{0x0f00701c,0x01020000},
{0x0f007020,0x04020107},
{0x0f007024,0x00000007},
{0x0f007028,0x02020200},
{0x0f00702c,0x0204040a},
{0x0f007030,0x04000000},
{0x0f007034,0x00000002},
{0x0f007038,0x1d060200},
{0x0f00703c,0x1c22221d},
{0x0f007040,0x8A116600},
{0x0f007044,0x222d0800},
{0x0f007048,0x02690204},
{0x0f00704c,0x00000000},
{0x0f007050,0x0100001c},
{0x0f007054,0x00000000},
{0x0f007058,0x00000000},
{0x0f00705c,0x00000000},
{0x0f007060,0x000A15D6},
{0x0f007064,0x0000000A},
{0x0f007068,0x00000000},
{0x0f00706c,0x00000001},
{0x0f007070,0x00004000},
{0x0f007074,0x00000000},
{0x0f007078,0x00000000},
{0x0f00707c,0x00000000},
{0x0f007080,0x00000000},
{0x0f007084,0x00000000},
{0x0f007088,0x01000001},
{0x0f00708c,0x00000101},
{0x0f007090,0x00000000},
{0x0f007094,0x00010000},
{0x0f007098,0x00000000},
{0x0F0070C8,0x00000104},
{0x0F007018,0x01010000}
};
int ddr_init(struct bcm_mini_adapter *Adapter)
{
struct bcm_ddr_setting *psDDRSetting=NULL;
ULONG RegCount=0;
UINT value = 0;
UINT uiResetValue = 0;
UINT uiClockSetting = 0;
int retval = STATUS_SUCCESS;
switch (Adapter->chip_id)
{
case 0xbece3200:
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting=asT3LP_DDRSetting80MHz;
RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_100_MHZ:
psDDRSetting=asT3LP_DDRSetting100MHz;
RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_133_MHZ:
psDDRSetting=asT3LP_DDRSetting133MHz;
RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
sizeof(struct bcm_ddr_setting));
if(Adapter->bMipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x03F13652;
}
else
{
uiClockSetting = 0x03F1365B;
}
break;
default:
return -EINVAL;
}
break;
case T3LPB:
case BCS220_2:
case BCS220_2BC:
case BCS250_BC:
case BCS220_3 :
/* Set bit 2 and bit 6 to 1 for BBIC 2mA drive
* (please check current value and additionally set these bits)
*/
if( (Adapter->chip_id != BCS220_2) &&
(Adapter->chip_id != BCS220_2BC) &&
(Adapter->chip_id != BCS220_3) )
{
retval= rdmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue |= 0x44;
retval = wrmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, WRM, DBG_LVL_ALL, "%s:%d WRM failed\n", __FUNCTION__, __LINE__);
return retval;
}
}
switch(Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3LPB_DDRSetting80MHz;
RegCount=(sizeof(asT3B_DDRSetting80MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_100_MHZ:
psDDRSetting=asT3LPB_DDRSetting100MHz;
RegCount=(sizeof(asT3B_DDRSetting100MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_133_MHZ:
psDDRSetting = asT3LPB_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
sizeof(struct bcm_ddr_setting));
if(Adapter->bMipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x03F13652;
}
else
{
uiClockSetting = 0x03F1365B;
}
break;
case DDR_160_MHZ:
psDDRSetting = asT3LPB_DDRSetting160MHz;
RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(struct bcm_ddr_setting);
if(Adapter->bMipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x03F137D2;
}
else
{
uiClockSetting = 0x03F137DB;
}
}
break;
case 0xbece0110:
case 0xbece0120:
case 0xbece0121:
case 0xbece0130:
case 0xbece0300:
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "DDR Setting: %x\n", Adapter->DDRSetting);
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3_DDRSetting80MHz;
RegCount = (sizeof(asT3_DDRSetting80MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_100_MHZ:
psDDRSetting = asT3_DDRSetting100MHz;
RegCount = (sizeof(asT3_DDRSetting100MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_133_MHZ:
psDDRSetting = asT3_DDRSetting133MHz;
RegCount = (sizeof(asT3_DDRSetting133MHz)/
sizeof(struct bcm_ddr_setting));
break;
default:
return -EINVAL;
}
case 0xbece0310:
{
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3B_DDRSetting80MHz;
RegCount=(sizeof(asT3B_DDRSetting80MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_100_MHZ:
psDDRSetting=asT3B_DDRSetting100MHz;
RegCount=(sizeof(asT3B_DDRSetting100MHz)/
sizeof(struct bcm_ddr_setting));
break;
case DDR_133_MHZ:
if(Adapter->bDPLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
{
memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
sizeof(asDPLL_266MHZ));
psDDRSetting = asT3B_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
sizeof(struct bcm_ddr_setting));
}
else
{
psDDRSetting = asT3B_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
sizeof(struct bcm_ddr_setting));
if(Adapter->bMipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x07F13652;
}
else
{
uiClockSetting = 0x07F1365B;
}
}
break;
default:
return -EINVAL;
}
break;
}
default:
return -EINVAL;
}
value=0;
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "Register Count is =%lu\n", RegCount);
while(RegCount && !retval)
{
if(uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
{
value = uiClockSetting;
}
else
{
value = psDDRSetting->ulRegValue;
}
retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, &value, sizeof(value));
if(STATUS_SUCCESS != retval) {
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
break;
}
RegCount--;
psDDRSetting++;
}
if(Adapter->chip_id >= 0xbece3300 )
{
mdelay(3);
if( (Adapter->chip_id != BCS220_2)&&
(Adapter->chip_id != BCS220_2BC)&&
(Adapter->chip_id != BCS220_3))
{
/* drive MDDR to half in case of UMA-B: */
uiResetValue = 0x01010001;
retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x00040020;
retval = wrmalt(Adapter, (UINT)0x0F007094, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x01020101;
retval = wrmalt(Adapter, (UINT)0x0F00701c, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x01010000;
retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
}
mdelay(3);
/* DC/DC standby change...
* This is to be done only for Hybrid PMU mode.
* with the current h/w there is no way to detect this.
* and since we dont have internal PMU lets do it under UMA-B chip id.
* we will change this when we will have internal PMU.
*/
if(Adapter->PmuMode == HYBRID_MODE_7C)
{
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x1322a8;
retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x132296;
retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
}
else if(Adapter->PmuMode == HYBRID_MODE_6 )
{
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x6003229a;
retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
uiResetValue = 0x1322a8;
retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
if(retval < 0) {
BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
return retval;
}
}
}
Adapter->bDDRInitDone = TRUE;
return retval;
}
int download_ddr_settings(struct bcm_mini_adapter *Adapter)
{
struct bcm_ddr_setting *psDDRSetting=NULL;
ULONG RegCount=0;
unsigned long ul_ddr_setting_load_addr = DDR_DUMP_INTERNAL_DEVICE_MEMORY;
UINT value = 0;
int retval = STATUS_SUCCESS;
BOOLEAN bOverrideSelfRefresh = FALSE;
switch (Adapter->chip_id)
{
case 0xbece3200:
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3LP_DDRSetting80MHz;
RegCount = ARRAY_SIZE(asT3LP_DDRSetting80MHz);
RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
break;
case DDR_100_MHZ:
psDDRSetting = asT3LP_DDRSetting100MHz;
RegCount = ARRAY_SIZE(asT3LP_DDRSetting100MHz);
RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
break;
case DDR_133_MHZ:
bOverrideSelfRefresh = TRUE;
psDDRSetting = asT3LP_DDRSetting133MHz;
RegCount = ARRAY_SIZE(asT3LP_DDRSetting133MHz);
RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
break;
default:
return -EINVAL;
}
break;
case T3LPB:
case BCS220_2:
case BCS220_2BC:
case BCS250_BC:
case BCS220_3 :
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3LPB_DDRSetting80MHz;
RegCount=ARRAY_SIZE(asT3LPB_DDRSetting80MHz);
RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
break;
case DDR_100_MHZ:
psDDRSetting = asT3LPB_DDRSetting100MHz;
RegCount = ARRAY_SIZE(asT3LPB_DDRSetting100MHz);
RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
break;
case DDR_133_MHZ:
bOverrideSelfRefresh = TRUE;
psDDRSetting = asT3LPB_DDRSetting133MHz;
RegCount = ARRAY_SIZE(asT3LPB_DDRSetting133MHz);
RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
break;
case DDR_160_MHZ:
bOverrideSelfRefresh = TRUE;
psDDRSetting = asT3LPB_DDRSetting160MHz;
RegCount = ARRAY_SIZE(asT3LPB_DDRSetting160MHz);
RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
break;
default:
return -EINVAL;
}
break;
case 0xbece0300:
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3_DDRSetting80MHz;
RegCount = ARRAY_SIZE(asT3_DDRSetting80MHz);
RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
break;
case DDR_100_MHZ:
psDDRSetting = asT3_DDRSetting100MHz;
RegCount = ARRAY_SIZE(asT3_DDRSetting100MHz);
RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
break;
case DDR_133_MHZ:
psDDRSetting = asT3_DDRSetting133MHz;
RegCount = ARRAY_SIZE(asT3_DDRSetting133MHz);
RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
break;
default:
return -EINVAL;
}
break;
case 0xbece0310:
{
switch (Adapter->DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3B_DDRSetting80MHz;
RegCount = ARRAY_SIZE(asT3B_DDRSetting80MHz);
RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
break;
case DDR_100_MHZ:
psDDRSetting = asT3B_DDRSetting100MHz;
RegCount = ARRAY_SIZE(asT3B_DDRSetting100MHz);
RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
break;
case DDR_133_MHZ:
bOverrideSelfRefresh = TRUE;
psDDRSetting = asT3B_DDRSetting133MHz;
RegCount = ARRAY_SIZE(asT3B_DDRSetting133MHz);
RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
break;
}
break;
}
default:
return -EINVAL;
}
//total number of Register that has to be dumped
value =RegCount ;
retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
if(retval)
{
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
return retval;
}
ul_ddr_setting_load_addr+=sizeof(ULONG);
/*signature */
value =(0x1d1e0dd0);
retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
if(retval)
{
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
return retval;
}
ul_ddr_setting_load_addr+=sizeof(ULONG);
RegCount*=(sizeof(struct bcm_ddr_setting)/sizeof(ULONG));
while(RegCount && !retval)
{
value = psDDRSetting->ulRegAddress ;
retval = wrmalt( Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
ul_ddr_setting_load_addr+=sizeof(ULONG);
if(!retval)
{
if(bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018))
{
value = (psDDRSetting->ulRegValue |(1<<8));
if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr,
&value, sizeof(value))){
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
break;
}
}
else
{
value = psDDRSetting->ulRegValue;
if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr ,
&value, sizeof(value))){
BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
break;
}
}
}
ul_ddr_setting_load_addr+=sizeof(ULONG);
RegCount--;
psDDRSetting++;
}
return retval;
}
|
