1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Hisilicon Hi6220 reset controller driver
*
* Copyright (c) 2016 Linaro Limited.
* Copyright (c) 2015-2016 HiSilicon Limited.
*
* Author: Feng Chen <puck.chen@hisilicon.com>
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/reset-controller.h>
#include <linux/reset.h>
#include <linux/platform_device.h>
#define PERIPH_ASSERT_OFFSET 0x300
#define PERIPH_DEASSERT_OFFSET 0x304
#define PERIPH_MAX_INDEX 0x509
#define SC_MEDIA_RSTEN 0x052C
#define SC_MEDIA_RSTDIS 0x0530
#define MEDIA_MAX_INDEX 8
#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
enum hi6220_reset_ctrl_type {
PERIPHERAL,
MEDIA,
AO,
};
struct hi6220_reset_data {
struct reset_controller_dev rc_dev;
struct regmap *regmap;
};
static int hi6220_peripheral_assert(struct reset_controller_dev *rc_dev,
unsigned long idx)
{
struct hi6220_reset_data *data = to_reset_data(rc_dev);
struct regmap *regmap = data->regmap;
u32 bank = idx >> 8;
u32 offset = idx & 0xff;
u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10;
return regmap_write(regmap, reg, BIT(offset));
}
static int hi6220_peripheral_deassert(struct reset_controller_dev *rc_dev,
unsigned long idx)
{
struct hi6220_reset_data *data = to_reset_data(rc_dev);
struct regmap *regmap = data->regmap;
u32 bank = idx >> 8;
u32 offset = idx & 0xff;
u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10;
return regmap_write(regmap, reg, BIT(offset));
}
static const struct reset_control_ops hi6220_peripheral_reset_ops = {
.assert = hi6220_peripheral_assert,
.deassert = hi6220_peripheral_deassert,
};
static int hi6220_media_assert(struct reset_controller_dev *rc_dev,
unsigned long idx)
{
struct hi6220_reset_data *data = to_reset_data(rc_dev);
struct regmap *regmap = data->regmap;
return regmap_write(regmap, SC_MEDIA_RSTEN, BIT(idx));
}
static int hi6220_media_deassert(struct reset_controller_dev *rc_dev,
unsigned long idx)
{
struct hi6220_reset_data *data = to_reset_data(rc_dev);
struct regmap *regmap = data->regmap;
return regmap_write(regmap, SC_MEDIA_RSTDIS, BIT(idx));
}
static const struct reset_control_ops hi6220_media_reset_ops = {
.assert = hi6220_media_assert,
.deassert = hi6220_media_deassert,
};
#define AO_SCTRL_SC_PW_CLKEN0 0x800
#define AO_SCTRL_SC_PW_CLKDIS0 0x804
#define AO_SCTRL_SC_PW_RSTEN0 0x810
#define AO_SCTRL_SC_PW_RSTDIS0 0x814
#define AO_SCTRL_SC_PW_ISOEN0 0x820
#define AO_SCTRL_SC_PW_ISODIS0 0x824
#define AO_MAX_INDEX 12
static int hi6220_ao_assert(struct reset_controller_dev *rc_dev,
unsigned long idx)
{
struct hi6220_reset_data *data = to_reset_data(rc_dev);
struct regmap *regmap = data->regmap;
int ret;
ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx));
if (ret)
return ret;
ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx));
if (ret)
return ret;
ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx));
return ret;
}
static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev,
unsigned long idx)
{
struct hi6220_reset_data *data = to_reset_data(rc_dev);
struct regmap *regmap = data->regmap;
int ret;
/*
* It was suggested to disable isolation before enabling
* the clocks and deasserting reset, to avoid glitches.
* But this order is preserved to keep it matching the
* vendor code.
*/
ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx));
if (ret)
return ret;
ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx));
if (ret)
return ret;
ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx));
return ret;
}
static const struct reset_control_ops hi6220_ao_reset_ops = {
.assert = hi6220_ao_assert,
.deassert = hi6220_ao_deassert,
};
static int hi6220_reset_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
enum hi6220_reset_ctrl_type type;
struct hi6220_reset_data *data;
struct regmap *regmap;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
type = (enum hi6220_reset_ctrl_type)of_device_get_match_data(dev);
regmap = syscon_node_to_regmap(np);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to get reset controller regmap\n");
return PTR_ERR(regmap);
}
data->regmap = regmap;
data->rc_dev.of_node = np;
if (type == MEDIA) {
data->rc_dev.ops = &hi6220_media_reset_ops;
data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
} else if (type == PERIPHERAL) {
data->rc_dev.ops = &hi6220_peripheral_reset_ops;
data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
} else {
data->rc_dev.ops = &hi6220_ao_reset_ops;
data->rc_dev.nr_resets = AO_MAX_INDEX;
}
return reset_controller_register(&data->rc_dev);
}
static const struct of_device_id hi6220_reset_match[] = {
{
.compatible = "hisilicon,hi6220-sysctrl",
.data = (void *)PERIPHERAL,
},
{
.compatible = "hisilicon,hi6220-mediactrl",
.data = (void *)MEDIA,
},
{
.compatible = "hisilicon,hi6220-aoctrl",
.data = (void *)AO,
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, hi6220_reset_match);
static struct platform_driver hi6220_reset_driver = {
.probe = hi6220_reset_probe,
.driver = {
.name = "reset-hi6220",
.of_match_table = hi6220_reset_match,
},
};
static int __init hi6220_reset_init(void)
{
return platform_driver_register(&hi6220_reset_driver);
}
postcore_initcall(hi6220_reset_init);
MODULE_LICENSE("GPL v2");
|
