1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
|
/*
* Intel Core SoC Power Management Controller Driver
*
* Copyright (c) 2016, Intel Corporation.
* All Rights Reserved.
*
* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <linux/seq_file.h>
#include <asm/cpu_device_id.h>
#include <asm/pmc_core.h>
#include "intel_pmc_core.h"
static struct pmc_dev pmc;
static const struct pci_device_id pmc_pci_ids[] = {
{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), (kernel_ulong_t)NULL },
{ 0, },
};
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
{
return readl(pmcdev->regbase + reg_offset);
}
static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
{
return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
}
/**
* intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
* @data: Out param that contains current SLP_S0 count.
*
* This API currently supports Intel Skylake SoC and Sunrise
* Point Platform Controller Hub. Future platform support
* should be added for platforms that support low power modes
* beyond Package C10 state.
*
* SLP_S0_RESIDENCY counter counts in 100 us granularity per
* step hence function populates the multiplied value in out
* parameter @data.
*
* Return: an error code or 0 on success.
*/
int intel_pmc_slp_s0_counter_read(u32 *data)
{
struct pmc_dev *pmcdev = &pmc;
u32 value;
if (!pmcdev->has_slp_s0_res)
return -EACCES;
value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
*data = pmc_core_adjust_slp_s0_step(value);
return 0;
}
EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
#if IS_ENABLED(CONFIG_DEBUG_FS)
static int pmc_core_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmcdev = s->private;
u32 counter_val;
counter_val = pmc_core_reg_read(pmcdev,
SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
seq_printf(s, "%u\n", pmc_core_adjust_slp_s0_step(counter_val));
return 0;
}
static int pmc_core_dev_state_open(struct inode *inode, struct file *file)
{
return single_open(file, pmc_core_dev_state_show, inode->i_private);
}
static const struct file_operations pmc_core_dev_state_ops = {
.open = pmc_core_dev_state_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
debugfs_remove_recursive(pmcdev->dbgfs_dir);
}
static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
struct dentry *dir, *file;
dir = debugfs_create_dir("pmc_core", NULL);
if (!dir)
return -ENOMEM;
pmcdev->dbgfs_dir = dir;
file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
dir, pmcdev, &pmc_core_dev_state_ops);
if (!file) {
pmc_core_dbgfs_unregister(pmcdev);
return -ENODEV;
}
return 0;
}
#else
static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
return 0;
}
static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
}
#endif /* CONFIG_DEBUG_FS */
static const struct x86_cpu_id intel_pmc_core_ids[] = {
{ X86_VENDOR_INTEL, 6, 0x4e, X86_FEATURE_MWAIT,
(kernel_ulong_t)NULL}, /* Skylake CPUID Signature */
{ X86_VENDOR_INTEL, 6, 0x5e, X86_FEATURE_MWAIT,
(kernel_ulong_t)NULL}, /* Skylake CPUID Signature */
{}
};
static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct device *ptr_dev = &dev->dev;
struct pmc_dev *pmcdev = &pmc;
const struct x86_cpu_id *cpu_id;
int err;
cpu_id = x86_match_cpu(intel_pmc_core_ids);
if (!cpu_id) {
dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
return -EINVAL;
}
err = pcim_enable_device(dev);
if (err < 0) {
dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
return err;
}
err = pci_read_config_dword(dev,
SPT_PMC_BASE_ADDR_OFFSET,
&pmcdev->base_addr);
if (err < 0) {
dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
return err;
}
dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
pmcdev->base_addr,
SPT_PMC_MMIO_REG_LEN);
if (!pmcdev->regbase) {
dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
return -ENOMEM;
}
err = pmc_core_dbgfs_register(pmcdev);
if (err < 0) {
dev_err(&dev->dev, "PMC Core: debugfs register failed.\n");
return err;
}
pmc.has_slp_s0_res = true;
return 0;
}
static struct pci_driver intel_pmc_core_driver = {
.name = "intel_pmc_core",
.id_table = pmc_pci_ids,
.probe = pmc_core_probe,
};
builtin_pci_driver(intel_pmc_core_driver);
|
