1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
|
#ifndef B43_XMIT_H_
#define B43_XMIT_H_
#include "main.h"
#define _b43_declare_plcp_hdr(size) \
struct b43_plcp_hdr##size { \
union { \
__le32 data; \
__u8 raw[size]; \
} __attribute__((__packed__)); \
} __attribute__((__packed__))
/* struct b43_plcp_hdr4 */
_b43_declare_plcp_hdr(4);
/* struct b43_plcp_hdr6 */
_b43_declare_plcp_hdr(6);
#undef _b43_declare_plcp_hdr
/* TX header for v4 firmware */
struct b43_txhdr_fw4 {
__le32 mac_ctl; /* MAC TX control */
__le16 mac_frame_ctl; /* Copy of the FrameControl field */
__le16 tx_fes_time_norm; /* TX FES Time Normal */
__le16 phy_ctl; /* PHY TX control */
__le16 phy_ctl_0; /* Unused */
__le16 phy_ctl_1; /* Unused */
__le16 phy_ctl_rts_0; /* Unused */
__le16 phy_ctl_rts_1; /* Unused */
__u8 phy_rate; /* PHY rate */
__u8 phy_rate_rts; /* PHY rate for RTS/CTS */
__u8 extra_ft; /* Extra Frame Types */
__u8 chan_radio_code; /* Channel Radio Code */
__u8 iv[16]; /* Encryption IV */
__u8 tx_receiver[6]; /* TX Frame Receiver address */
__le16 tx_fes_time_fb; /* TX FES Time Fallback */
struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */
__le16 rts_dur_fb; /* RTS fallback duration */
struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP */
__le16 dur_fb; /* Fallback duration */
__le16 mm_dur_time; /* Unused */
__le16 mm_dur_time_fb; /* Unused */
__le32 time_stamp; /* Timestamp */
PAD_BYTES(2);
__le16 cookie; /* TX frame cookie */
__le16 tx_status; /* TX status */
struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP */
__u8 rts_frame[16]; /* The RTS frame (if used) */
PAD_BYTES(2);
struct b43_plcp_hdr6 plcp; /* Main PLCP */
} __attribute__ ((__packed__));
/* MAC TX control */
#define B43_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
#define B43_TX4_MAC_KEYIDX_SHIFT 20
#define B43_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
#define B43_TX4_MAC_KEYALG_SHIFT 16
#define B43_TX4_MAC_LIFETIME 0x00001000
#define B43_TX4_MAC_FRAMEBURST 0x00000800
#define B43_TX4_MAC_SENDCTS 0x00000400
#define B43_TX4_MAC_AMPDU 0x00000300
#define B43_TX4_MAC_AMPDU_SHIFT 8
#define B43_TX4_MAC_5GHZ 0x00000080
#define B43_TX4_MAC_IGNPMQ 0x00000020
#define B43_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
#define B43_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
#define B43_TX4_MAC_SENDRTS 0x00000004
#define B43_TX4_MAC_LONGFRAME 0x00000002
#define B43_TX4_MAC_ACK 0x00000001
/* Extra Frame Types */
#define B43_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */
#define B43_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
#define B43_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
/* PHY TX control word */
#define B43_TX4_PHY_OFDM 0x0001 /* Data frame rate type */
#define B43_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
#define B43_TX4_PHY_ANT 0x03C0 /* Antenna selection */
#define B43_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
#define B43_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
#define B43_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
void b43_generate_txhdr(struct b43_wldev *dev,
u8 * txhdr,
const unsigned char *fragment_data,
unsigned int fragment_len,
const struct ieee80211_tx_control *txctl, u16 cookie);
/* Transmit Status */
struct b43_txstatus {
u16 cookie; /* The cookie from the txhdr */
u16 seq; /* Sequence number */
u8 phy_stat; /* PHY TX status */
u8 frame_count; /* Frame transmit count */
u8 rts_count; /* RTS transmit count */
u8 supp_reason; /* Suppression reason */
/* flags */
u8 pm_indicated; /* PM mode indicated to AP */
u8 intermediate; /* Intermediate status notification (not final) */
u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
u8 acked; /* Wireless ACK received */
};
/* txstatus supp_reason values */
enum {
B43_TXST_SUPP_NONE, /* Not suppressed */
B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
B43_TXST_SUPP_PREV, /* Previous fragment failed */
B43_TXST_SUPP_CHAN, /* Channel mismatch */
B43_TXST_SUPP_LIFE, /* Lifetime expired */
B43_TXST_SUPP_UNDER, /* Buffer underflow */
B43_TXST_SUPP_ABNACK, /* Afterburner NACK */
};
/* Transmit Status as received through DMA/PIO on old chips */
struct b43_hwtxstatus {
PAD_BYTES(4);
__le16 cookie;
u8 flags;
u8 count;
PAD_BYTES(2);
__le16 seq;
u8 phy_stat;
PAD_BYTES(1);
} __attribute__ ((__packed__));
/* Receive header for v4 firmware. */
struct b43_rxhdr_fw4 {
__le16 frame_len; /* Frame length */
PAD_BYTES(2);
__le16 phy_status0; /* PHY RX Status 0 */
__u8 jssi; /* PHY RX Status 1: JSSI */
__u8 sig_qual; /* PHY RX Status 1: Signal Quality */
__le16 phy_status2; /* PHY RX Status 2 */
__le16 phy_status3; /* PHY RX Status 3 */
__le32 mac_status; /* MAC RX status */
__le16 mac_time;
__le16 channel;
} __attribute__ ((__packed__));
/* PHY RX Status 0 */
#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
#define B43_RX_PHYST0_PLCPHCF 0x0200
#define B43_RX_PHYST0_PLCPFV 0x0100
#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
#define B43_RX_PHYST0_LCRS 0x0040
#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
#define B43_RX_PHYST0_UNSRATE 0x0010
#define B43_RX_PHYST0_CLIP 0x000C
#define B43_RX_PHYST0_CLIP_SHIFT 2
#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
/* PHY RX Status 2 */
#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
#define B43_RX_PHYST2_LNAG_SHIFT 14
#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
#define B43_RX_PHYST2_PNAG_SHIFT 10
#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
/* PHY RX Status 3 */
#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
#define B43_RX_PHYST3_DIGG_SHIFT 11
#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
/* MAC RX Status */
#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
#define B43_RX_MAC_AGGTYPE_SHIFT 17
#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
#define B43_RX_MAC_KEYIDX_SHIFT 5
#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
/* RX channel */
#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
#define B43_RX_CHAN_ID_SHIFT 3
#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */
u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
const u16 octets, const u8 bitrate);
void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
void b43_handle_txstatus(struct b43_wldev *dev,
const struct b43_txstatus *status);
void b43_handle_hwtxstatus(struct b43_wldev *dev,
const struct b43_hwtxstatus *hw);
void b43_tx_suspend(struct b43_wldev *dev);
void b43_tx_resume(struct b43_wldev *dev);
#define B43_NR_QOSPARMS 22
enum {
B43_QOSPARM_TXOP = 0,
B43_QOSPARM_CWMIN,
B43_QOSPARM_CWMAX,
B43_QOSPARM_CWCUR,
B43_QOSPARM_AIFS,
B43_QOSPARM_BSLOTS,
B43_QOSPARM_REGGAP,
B43_QOSPARM_STATUS,
};
void b43_qos_init(struct b43_wldev *dev);
/* Helper functions for converting the key-table index from "firmware-format"
* to "raw-format" and back. The firmware API changed for this at some revision.
* We need to account for that here. */
static inline int b43_new_kidx_api(struct b43_wldev *dev)
{
/* FIXME: Not sure the change was at rev 351 */
return (dev->fw.rev >= 351);
}
static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
{
u8 firmware_kidx;
if (b43_new_kidx_api(dev)) {
firmware_kidx = raw_kidx;
} else {
if (raw_kidx >= 4) /* Is per STA key? */
firmware_kidx = raw_kidx - 4;
else
firmware_kidx = raw_kidx; /* TX default key */
}
return firmware_kidx;
}
static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
{
u8 raw_kidx;
if (b43_new_kidx_api(dev))
raw_kidx = firmware_kidx;
else
raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
return raw_kidx;
}
#endif /* B43_XMIT_H_ */
|
