blob: 1cf252e7309a4ad4eb1eaef0d6f4fabc1124a4b4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2013-2019 NVIDIA Corporation.
* Copyright (C) 2015 Rob Clark
*/
#ifndef DRM_TEGRA_DP_H
#define DRM_TEGRA_DP_H 1
struct drm_dp_aux;
#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
/**
* struct drm_dp_link - DP link capabilities
* @revision: DP specification revision supported on the link
* @rate: maximum clock rate supported on the link
* @num_lanes: maximum number of lanes supported on the link
* @capabilities: bitmask of capabilities supported on the link
*/
struct drm_dp_link {
unsigned char revision;
unsigned int rate;
unsigned int num_lanes;
unsigned long capabilities;
};
int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
#endif
|
