1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
|
// SPDX-License-Identifier: GPL-2.0
/*
* FPGA Freeze Bridge Controller
*
* Copyright (C) 2016 Altera Corporation. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/fpga/fpga-bridge.h>
#define FREEZE_CSR_STATUS_OFFSET 0
#define FREEZE_CSR_CTRL_OFFSET 4
#define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8
#define FREEZE_CSR_REG_VERSION 12
#define FREEZE_CSR_SUPPORTED_VERSION 2
#define FREEZE_CSR_OFFICIAL_VERSION 0xad000003
#define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0)
#define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
#define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0)
#define FREEZE_CSR_CTRL_RESET_REQ BIT(1)
#define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2)
#define FREEZE_BRIDGE_NAME "freeze"
struct altera_freeze_br_data {
struct device *dev;
void __iomem *base_addr;
bool enable;
};
/*
* Poll status until status bit is set or we have a timeout.
*/
static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
u32 timeout, u32 req_ack)
{
struct device *dev = priv->dev;
void __iomem *csr_illegal_req_addr = priv->base_addr +
FREEZE_CSR_ILLEGAL_REQ_OFFSET;
u32 status, illegal, ctrl;
int ret = -ETIMEDOUT;
do {
illegal = readl(csr_illegal_req_addr);
if (illegal) {
dev_err(dev, "illegal request detected 0x%x", illegal);
writel(1, csr_illegal_req_addr);
illegal = readl(csr_illegal_req_addr);
if (illegal)
dev_err(dev, "illegal request not cleared 0x%x",
illegal);
ret = -EINVAL;
break;
}
status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
status &= req_ack;
if (status) {
ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
dev_dbg(dev, "%s request %x acknowledged %x %x\n",
__func__, req_ack, status, ctrl);
ret = 0;
break;
}
udelay(1);
} while (timeout--);
if (ret == -ETIMEDOUT)
dev_err(dev, "%s timeout waiting for 0x%x\n",
__func__, req_ack);
return ret;
}
static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
u32 timeout)
{
struct device *dev = priv->dev;
void __iomem *csr_ctrl_addr = priv->base_addr +
FREEZE_CSR_CTRL_OFFSET;
u32 status;
int ret;
status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
dev_dbg(dev, "%s bridge already disabled %d\n",
__func__, status);
return 0;
} else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
return -EINVAL;
}
writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
ret = altera_freeze_br_req_ack(priv, timeout,
FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
if (ret)
writel(0, csr_ctrl_addr);
else
writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
return ret;
}
static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
u32 timeout)
{
struct device *dev = priv->dev;
void __iomem *csr_ctrl_addr = priv->base_addr +
FREEZE_CSR_CTRL_OFFSET;
u32 status;
int ret;
writel(0, csr_ctrl_addr);
status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
dev_dbg(dev, "%s bridge already enabled %d\n",
__func__, status);
return 0;
} else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
return -EINVAL;
}
writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
ret = altera_freeze_br_req_ack(priv, timeout,
FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
writel(0, csr_ctrl_addr);
return ret;
}
/*
* enable = 1 : allow traffic through the bridge
* enable = 0 : disable traffic through the bridge
*/
static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
bool enable)
{
struct altera_freeze_br_data *priv = bridge->priv;
struct fpga_image_info *info = bridge->info;
u32 timeout = 0;
int ret;
if (enable) {
if (info)
timeout = info->enable_timeout_us;
ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
} else {
if (info)
timeout = info->disable_timeout_us;
ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
}
if (!ret)
priv->enable = enable;
return ret;
}
static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
{
struct altera_freeze_br_data *priv = bridge->priv;
return priv->enable;
}
static const struct fpga_bridge_ops altera_freeze_br_br_ops = {
.enable_set = altera_freeze_br_enable_set,
.enable_show = altera_freeze_br_enable_show,
};
static const struct of_device_id altera_freeze_br_of_match[] = {
{ .compatible = "altr,freeze-bridge-controller", },
{},
};
MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
static int altera_freeze_br_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
void __iomem *base_addr;
struct altera_freeze_br_data *priv;
struct fpga_bridge *br;
struct resource *res;
u32 status, revision;
if (!np)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(dev, res);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
revision = readl(base_addr + FREEZE_CSR_REG_VERSION);
if ((revision != FREEZE_CSR_SUPPORTED_VERSION) &&
(revision != FREEZE_CSR_OFFICIAL_VERSION)) {
dev_err(dev,
"%s unexpected revision 0x%x != 0x%x != 0x%x\n",
__func__, revision, FREEZE_CSR_SUPPORTED_VERSION,
FREEZE_CSR_OFFICIAL_VERSION);
return -EINVAL;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
status = readl(base_addr + FREEZE_CSR_STATUS_OFFSET);
if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
priv->enable = 1;
priv->base_addr = base_addr;
br = devm_fpga_bridge_create(dev, FREEZE_BRIDGE_NAME,
&altera_freeze_br_br_ops, priv);
if (!br)
return -ENOMEM;
platform_set_drvdata(pdev, br);
return fpga_bridge_register(br);
}
static int altera_freeze_br_remove(struct platform_device *pdev)
{
struct fpga_bridge *br = platform_get_drvdata(pdev);
fpga_bridge_unregister(br);
return 0;
}
static struct platform_driver altera_freeze_br_driver = {
.probe = altera_freeze_br_probe,
.remove = altera_freeze_br_remove,
.driver = {
.name = "altera_freeze_br",
.of_match_table = of_match_ptr(altera_freeze_br_of_match),
},
};
module_platform_driver(altera_freeze_br_driver);
MODULE_DESCRIPTION("Altera Freeze Bridge");
MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
MODULE_LICENSE("GPL v2");
|
