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|
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/jz4780-cgu.h>
#include <dt-bindings/dma/jz4780-dma.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ingenic,jz4780";
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
intc: interrupt-controller@10001000 {
compatible = "ingenic,jz4780-intc";
reg = <0x10001000 0x50>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
ext: ext {
compatible = "fixed-clock";
#clock-cells = <0>;
};
rtc: rtc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
cgu: jz4780-cgu@10000000 {
compatible = "ingenic,jz4780-cgu";
reg = <0x10000000 0x100>;
clocks = <&ext>, <&rtc>;
clock-names = "ext", "rtc";
#clock-cells = <1>;
};
tcu: timer@10002000 {
compatible = "ingenic,jz4780-tcu",
"ingenic,jz4770-tcu",
"simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4780_CLK_RTCLK
&cgu JZ4780_CLK_EXCLK
&cgu JZ4780_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <27 26 25>;
};
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4780-rtc";
reg = <0x10003000 0x4c>;
interrupt-parent = <&intc>;
interrupts = <32>;
clocks = <&cgu JZ4780_CLK_RTCLK>;
clock-names = "rtc";
};
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4780-pinctrl";
reg = <0x10010000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4780-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <17>;
};
gpb: gpio@1 {
compatible = "ingenic,jz4780-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <16>;
};
gpc: gpio@2 {
compatible = "ingenic,jz4780-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <15>;
};
gpd: gpio@3 {
compatible = "ingenic,jz4780-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
gpe: gpio@4 {
compatible = "ingenic,jz4780-gpio";
reg = <4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <13>;
};
gpf: gpio@5 {
compatible = "ingenic,jz4780-gpio";
reg = <5>;
gpio-controller;
gpio-ranges = <&pinctrl 0 160 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <12>;
};
};
spi_gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <2>;
gpio-miso = <&gpe 14 0>;
gpio-sck = <&gpe 15 0>;
gpio-mosi = <&gpe 17 0>;
cs-gpios = <&gpe 16 0
&gpe 18 0>;
spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>;
interrupt-parent = <&intc>;
interrupts = <51>;
clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
clock-names = "baud", "module";
status = "disabled";
};
uart1: serial@10031000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10031000 0x100>;
interrupt-parent = <&intc>;
interrupts = <50>;
clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
clock-names = "baud", "module";
status = "disabled";
};
uart2: serial@10032000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10032000 0x100>;
interrupt-parent = <&intc>;
interrupts = <49>;
clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
clock-names = "baud", "module";
status = "disabled";
};
uart3: serial@10033000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10033000 0x100>;
interrupt-parent = <&intc>;
interrupts = <48>;
clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
clock-names = "baud", "module";
status = "disabled";
};
uart4: serial@10034000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10034000 0x100>;
interrupt-parent = <&intc>;
interrupts = <34>;
clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
clock-names = "baud", "module";
status = "disabled";
};
watchdog: watchdog@10002000 {
compatible = "ingenic,jz4780-watchdog";
reg = <0x10002000 0x10>;
clocks = <&cgu JZ4780_CLK_RTCLK>;
clock-names = "rtc";
};
nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000
2 0 0x1a000000 0x1000000
3 0 0x19000000 0x1000000
4 0 0x18000000 0x1000000
5 0 0x17000000 0x1000000
6 0 0x16000000 0x1000000>;
clocks = <&cgu JZ4780_CLK_NEMC>;
status = "disabled";
};
dma: dma@13420000 {
compatible = "ingenic,jz4780-dma";
reg = <0x13420000 0x400
0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <10>;
clocks = <&cgu JZ4780_CLK_PDMA>;
};
mmc0: mmc@13450000 {
compatible = "ingenic,jz4780-mmc";
reg = <0x13450000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <37>;
clocks = <&cgu JZ4780_CLK_MSC0>;
clock-names = "mmc";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
<&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
dma-names = "rx", "tx";
status = "disabled";
};
mmc1: mmc@13460000 {
compatible = "ingenic,jz4780-mmc";
reg = <0x13460000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <36>;
clocks = <&cgu JZ4780_CLK_MSC1>;
clock-names = "mmc";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
<&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
dma-names = "rx", "tx";
status = "disabled";
};
bch: bch@134d0000 {
compatible = "ingenic,jz4780-bch";
reg = <0x134d0000 0x10000>;
clocks = <&cgu JZ4780_CLK_BCH>;
status = "disabled";
};
};
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